NDLI: An approach to the analysis and test of crosstalk faults in digital VLSI circuits

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An approach to the analysis and test of crosstalk faults in digital VLSI circuits

Content Provider	IEEE Xplore Digital Library
Author	Rubio, A. Itazaki, N. Xu, X. Kinoshita, K.
Copyright Year	1991
Description	Author affiliation: Dept. of Phys., Balearic Islands Univ., Palma, Spain (Rubio, A.; Itazaki, N.; Xu, X.; Kinoshita, K.)
Abstract	The continuous reduction of the device size in integrated circuits and the increasing of the switching rate cause parasitic capacitances between conducting layers which might become dominant enough to provoke logic errors in the circuits. So, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this sort of faults. This paper presents a logic fault characterization of these faults, a logic level circuit fault model, a crosstalk fault list generator working at layout level and a test pattern generation procedure for crosstalk type faults.<>
Starting Page	72
Ending Page	79
File Size	558798
Page Count	8
File Format	PDF
DOI	10.1109/EDAC.1991.206363
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-02-25
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Crosstalk Circuit faults Logic circuits Logic devices Logic testing Test pattern generators Circuit testing Switching circuits Parasitic capacitance Coupling circuits
Content Type	Text
Resource Type	Article

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