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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ross, D.E. Butler, K.M. Kapur, R. Mercer, M.R. |
| Copyright Year | 1991 |
| Description | Author affiliation: Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA (Ross, D.E.; Butler, K.M.; Kapur, R.; Mercer, M.R.) |
| Abstract | Symbolic simulation via ordered binary decision diagrams (OBDDs) is becoming more feasible each year. These representations are often very efficient under an appropriate ordering of the variables of the functions represented. Recently, heuristics for ordering variables have been developed, but due to the nature of heuristics, no single heuristic always produces an appropriate ordering. The authors develop and analyze a technique for selecting the best of several candidate orderings. The ordering selection method is fast. Its ranking of an ordering is compared to the actual performance of an ordering during functionals (OBDD) calculations in circuits from the ISCAS85 combinational benchmarks. Compared to any previously published single ordering heuristic, the method allows OBDD calculations using less cumulative memory over all six circuits investigated, and also produces over an order of magnitude improvement for one or more of these circuits, over every single heuristic examined.< |
| Starting Page | 4 |
| Ending Page | 10 |
| File Size | 679758 |
| Page Count | 7 |
| File Format | |
| DOI | 10.1109/EDAC.1991.206348 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1991-02-25 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuit simulation Logic circuits Computational modeling Computer simulation Data structures Boolean functions Cost function Logic design |
| Content Type | Text |
| Resource Type | Article |
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