NDLI: Delay fault models and test generation for random logic sequential circuits

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Delay fault models and test generation for random logic sequential circuits

Content Provider	IEEE Xplore Digital Library
Author	Chakraborty, T.J. Agrawal, V.D. Bushnell, M.L.
Copyright Year	1992
Description	Author affiliation: AT&T Bell Lab., Princeton, NJ, USA (Chakraborty, T.J.)
Abstract	The authors study the problem of delay fault modeling and test generation for any random logic sequential circuit. The proposed test generation method, based on transition and hazard states of signals, is applicable to any sequential circuit of either non-scan, scan or scan-hold type of design. Three fault models based on different initial state assumptions during the propagation of the fault effect to a primary output are proposed and analyzed using the proposed delay fault test generation method. A novel thirteen-value algebra is considered to simplify the analysis of robust and nonrobust tests during fault simulation of path delay faults.<>
Starting Page	165
Ending Page	172
File Size	701320
Page Count	8
File Format	PDF
ISBN	0818628227
ISSN	0738100X
DOI	10.1109/DAC.1992.227842
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-06-08
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic testing Sequential analysis Circuit faults Circuit testing Sequential circuits Signal generators Hazards Signal design Delay effects Propagation delay
Content Type	Text
Resource Type	Article

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