NDLI: CAD Framework Initiative-a user perspective

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2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

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Proceedings 37th Design Automation Conference

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[1992] Proceedings 29th ACM/IEEE Design Automation Conference

Certified timing verification and the transition delay of a logic circuit

The role of long and short paths in circuit performance optimization

Iterative and adaptive slack allocation for performance-driven layout and FPGA routing

FARM: an efficient feed-through pin assignment algorithm

Power and ground network topology optimization for cell based VLSIs

Zero skew clock net routing

Application-driven design automation for microprocessor design

Automated design decision support system

Design process management for CAD frameworks

A near optimal algorithm for technology mapping minimizing area under delay constraints

LATTIS: an iterative speedup heuristic for mapped logic

BDDMAP: a technology mapper based on a new covering algorithm

On the circuit implementation problem (combinatorial logic circuits)

IPDA: interconnect performance design assistant

Tools to aid in wiring rule generation for high speed interconnects

Challenges and advances in electrical interconnect analysis

Test-set preserving logic transformations

Optimization of primitive gate networks using multiple output two-level minimization

Efficient sum-to-one subsets algorithm for logic optimization

Coalgebraic division for multilevel logic synthesis

HLSIM-a new hierarchical logic simulator and netlist converter

Performance evaluation of an event-driven logic simulation machine

Zero delay versus positive delay in an incremental switch-level simulator

Two new techniques for compiled multi-delay logic simulation

Validating discrete event simulations using event pattern mappings

An approach to symbolic timing verification

On the temporal equivalence of sequential circuits

Computing optimal clock schedules

Analyzing cycle stealing on synchronous circuits with level-sensitive latches

Acquiring and maintaining state-of-the-art DA systems

An improved synthesis algorithm for multiplexor-based PGAs

Characterization of Boolean functions for rapid matching in EPGA technology mapping

Area and delay mapping for table-look-up based field programmable gate arrays

TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections

A novel approach to delay-fault diagnosis

Algorithms for current monitor based diagnosis of bridging and leakage faults

Exact evaluation of diagnostic test resolution

On the distribution of fault coverage and test length in random testing of combinational circuits

HOPE: an efficient parallel fault simulator

Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers

On efficient concurrent fault simulation for synchronous sequential circuits

A new hierarchical layout compactor using simplified graph models

Process independent constraint graph compaction

Hierarchical pitchmatching compaction using minimum design

An interpreter for general netlist design rule checking

Hcompare: a hierarchical netlist comparison program

Functional synthesis using area and delay optimization

ISIS: a system for performance driven resource sharing

Data path allocation using an extended binding model

Automatic test knowledge extraction from VHDL (ATKET)

Multipole-accelerated 3-D capacitance extraction algorithms for structures with conformal dielectrics

An integrated approach to realistic worst-case design optimization of MOS analog circuits

A mixed-integer nonlinear programming approach to analog circuit synthesis

Plane parallel A* maze router and its application to FPGAs

Experiments with a performance driven module generator

Routing considerations in symbolic layout synthesis

An efficient routing algorithm for SOG cell generation on a dense gate-isolated layout style

CAD Framework Initiative-a user perspective

The Electronic Design Interchange Format EDIF: present and future

Transformation-based high-level synthesis of fault-tolerant ASICs

Control optimization in high-level synthesis using behavioral don't cares

An efficient algorithm for microword length minimization

Distributed design-space exploration for high-level synthesis systems

Superpipelined control and data path synthesis

The automatic generation of bus-interface models

Inductive verification of iterative systems

Functional approaches to generating orderings for efficient symbolic representations

Exact calculation of synchronization sequences based on binary decision diagrams

A new model for improving symbolic product machine traversal

Edge-valued binary decision for multi-level hierarchical verification

Over-the-cell routers for new cell model

Over-the-cell channel routing for high performance circuits

A pin permutation algorithm for improving over-the-cell channel routing

New models for four- and five-layer channel routing

A multi-layer channel router with new style of over-the-cell routing

A new efficient approach to multilayer channel routing problem

State assignment using input/output functions

Solving the state assignment problem for signal transition graphs

Finite state machine synthesis with fault tolerant test function

Recurrence equations and the optimization of synchronous logic circuits

A methodology to reduce the computational cost of behavioral test pattern generation

Hierarchical test generation under intensive global functional constraints

Estimation of average switching activity in combinational and sequential circuits

Circuit enhancement by eliminating long false paths

Circuit structure relations to redundancy and delay: the KMS algorithm revisited

A path-oriented approach for reducing hazards in asynchronous designs

Partitioning by regularity extraction

High-level synthesis with pin constraints for multiple-chip designs

Synthesis and simulation of digital systems containing interacting hardware and software components

Specification partitioning for system design

AWEsymbolic: compiled analysis of linear(ized) circuits using asymptotic waveform evaluation

On the stability of moment-matching approximations in asymptotic waveform evaluation

Generalized moment-matching methods for transient analysis of interconnect networks

Synthesis from production-based specifications

High-level synthesis from VHDL with exact timing constraints

The Princeton University behavioral synthesis system

At-speed delay testing of synchronous sequential circuits

Equivalence of robust delay-fault and single stuck-fault test generation

Delay fault models and test generation for random logic sequential circuits

Delay fault test generation for scan/hold circuits using Boolean expressions

Fuzzy logic approach to placement problem

A performance driven macro-cell placement algorithm

APT: an area-performance-testability driven placement algorithm

High level synthesis of pipelined instruction set processors and back-end compilers

An engineering environment for hardware/software co-simulation

Time constrained allocation and assignment techniques for high throughput signal processing

Optimal allocation and binding in high-level synthesis

Optimal scheduling and allocation of embedded VLSI chips

Global scheduling independent of control dependencies based on condition vectors

Representing conditional branches for high-level synthesis applications

Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems

A boundary-element approach to transient simulation of three-dimensional integrated circuit interconnect

AWESpice: a general tool for the accurate and efficient simulation of interconnect problems

Transient simulation of lossy interconnect

Simulating lossy interconnect with high frequency nonidealities in linear time

Canonical embedding of rectangular duals with applications to VLSI floorplanning

A graph theoretic technique to speed up floorplan area optimization

A wire length estimation technique utilizing neighborhood density equations

Performance-driven system partitioning on multi-chip modules

Net partitions yield better module partitions

FPGA design principles

Symbolic prime generation for multiple-valued functions

Implicit and incremental computation of primes and essential primes of Boolean functions

Fast exact and quasi-minimal minimization of highly testable fixed-polarity AND/XOR canonical networks

SWiTEST: a switch level test generation system for CMOS combinational circuits

FREEZE: a new approach for testing sequential circuits

On the over-specification problem in sequential ATPG algorithms

Parallel waveform relaxation of circuits with global feedback loops

Incremental circuit simulation using waveform relaxation

Maximum current estimation in CMOS circuits

Proceedings. 29th ACM/IEEE Design Automation Conference (Cat. No.92CH3144-3)

28th ACM/IEEE Design Automation Conference

27th ACM/IEEE Design Automation Conference

26th ACM/IEEE Design Automation Conference

25th ACM/IEEE, Design Automation Conference.Proceedings 1988.

24th ACM/IEEE Design Automation Conference

23rd ACM/IEEE Design Automation Conference

22nd ACM/IEEE Design Automation Conference

21st Design Automation Conference Proceedings

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15th Design Automation Conference

30th ACM/IEEE Design Automation Conference

CAD Framework Initiative-a user perspective

Content Provider	IEEE Xplore Digital Library
Author	Scallan, T.J.
Copyright Year	1992
Description	Author affiliation: IBM Corp., Kingston, NY, USA (Scallan, T.J.)
Abstract	The author presents an overview of the CAD Framework Initiative (CFI) from a user's perspective. CFI is an industry consortium whose charter is to define interface standards that facilitate integration of design automation tools and design data for the benefit of end users and vendors worldwide. Integration problems faced by CAD users are introduced, followed by a discussion of the concept of a CAD framework. CFI's role in the evolution toward framework standardization is described. Specifically highlighted are key demonstrations of CFI's progress that have been conducted at the Design Automation Conference. End user benefits and expectations with respect to CFI are discussed.<>
Starting Page	672
Ending Page	675
File Size	337617
Page Count	4
File Format	PDF
ISBN	0818628227
ISSN	0738100X
DOI	10.1109/DAC.1992.227801
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-06-08
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design automation Standardization Design engineering Computer aided manufacturing Standards development Hardware Maintenance engineering Technical drawing Software design Manufacturing processes
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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