NDLI: Parallel code generation respecting allocation

Content Provider	IEEE Xplore Digital Library
Author	Slama, Y. Jemni, M. Feautrier, P.
Copyright Year	2003
Description	Author affiliation: Inf. Dept., FST, Tunis, Tunisia (Slama, Y.; Jemni, M.)
Abstract	Summary form only given. The general process of automatic program parallelization, first consists of determining the source program dependencies, then determining a parallel execution order of all the program operations. This turns out to determine a scheduling and/or an allocation, i.e. a function which associates to each operation, an execution date, and/or a processor number. Such a function is known as temporal transformation if it is a scheduling, a spatial one if it is an allocation, and a space/time transformation, if it is a combination of both. Then, synchronizations must be inserted to satisfy the dependencies between the statements assigned to different processors. Finally, the last stage of parallelization is the generation of the target parallel program, respecting the chosen transformation, and taking into account the target machine characteristics (processor number, memory architecture, etc.). There are many scheduling and allocation methods for polyhedral programs. However, few efficient methods have been devoted to code generation, namely those generating code from allocation. As the latter has generally the advantage of speed and good locality, we are interested in designing an allocation based method of code generation for a loop nest. The generated program has the structure of a nest involving an outer parallel loop enumerating processors and enclosing, in a serial order, the set of statements executed by the same processor.
Sponsorship	Arab Comput. Soc. IEEE Comput. Soc
File Size	42467
File Format	PDF
ISBN	0780379837
DOI	10.1109/AICCSA.2003.1227523
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-07-14
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Processor scheduling Character generation Memory architecture
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in