NDLI: Distributed parallel scheduling algorithms for high speed virtual output queuing switches

Content Provider	IEEE Xplore Digital Library
Author	Jing Liu Hamdi, M. Qingsheng Hu
Copyright Year	2003
Description	Author affiliation: Dept. of Comput. Sci., Hong Kong Univ. of Sci. & Technol., Kowloon, China (Jing Liu; Hamdi, M.; Qingsheng Hu)
Abstract	Summary form only given. We present a novel scalable scheduling architecture for input queued switches with virtual output queuing (VOQ) scheme and also proper high-performance arbitration algorithms for this architecture. In contrast to traditional switching architecture where the scheduler is implemented by one single centralized scheduling device, the proposed scheduling architecture connects several single scheduling devices in series and a distributed scheduling algorithm is run sequentially on them, whereby the inputs of each single scheduling device build connections to a group of outputs, considering both their local transmission requests as well as global output availability information. We show that a pipeline pattern can be used here to increase the efficiency of the scheduling scheme and the scheduling algorithms can be run in parallel on all the separate scheduling devices, which also guarantee the fairness of the scheduling. The advantage of this architecture is in its ability to construct a large scheduler with several small scheduling devices and offer high-performance scheduling as well. The parallel pipeline scheme yields a practical scalable solution for large port number switches. We first introduce a distributed parallel round robin scheduling algorithm (DPRR) for the proposed architecture. Through the analysis of simulation results on various admissible traffics, it is shown that the performance of DPRR is much better than or very close to the performance of other round robin scheduling algorithms used commonly on centralized schedulers. We also prove that under Bernoulli i.i.d. uniform traffic DPRR achieves 100% throughput. Second, we introduce a distributed parallel round robin scheduling algorithm with memory (DPRRM) as an improved version of DPRR to make it stable under any admissible traffic.
Sponsorship	Arab Comput. Soc. IEEE Comput. Soc
File Size	47347
File Format	PDF
ISBN	0780379837
DOI	10.1109/AICCSA.2003.1227461
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-07-14
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Scheduling algorithm Switches Round robin Pipelines Traffic control Availability Performance analysis Algorithm design and analysis Analytical models Throughput
Content Type	Text
Resource Type	Article

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