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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Subrahmanyam, P.A. |
| Copyright Year | 1987 |
| Description | Author affiliation: AT&T Bell Laboratories, Holmdel, NJ (Subrahmanyam, P.A.) |
| Abstract | This paper discusses the use of formal reasoning techniques to aid in the automated structural design of leaf cells, in the more global context of VLSI circuit design. The technique supports an encapsulation of the technology-dependent aspects of a design by using appropriate formal models, and guarantees the consistency of the designs produced with respect to the functional specification and the technology model employed. The approach is illustrated by its use in the design of some leaf cells in CMOS. The role of the techniques when used in an interactive mode and in the verification of existing designs is also discussed. |
| Starting Page | 459 |
| Ending Page | 465 |
| File Size | 1015675 |
| Page Count | 7 |
| File Format | |
| ISBN | 0818607815 |
| ISSN | 0738100X |
| DOI | 10.1109/DAC.1987.203282 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1987-06-28 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Synthesizers CMOS technology Circuit synthesis Very large scale integration Appropriate technology Semiconductor device modeling Permission Encapsulation Fabrication Process design |
| Content Type | Text |
| Resource Type | Article |
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