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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Adshead, H.G. |
| Copyright Year | 1982 |
| Description | Author affiliation: ICL Manchester, UK (Adshead, H.G.) |
| Abstract | With the increasing scale of integration we need to employ DA algorithms to assist us in managing the complexities involved. Many of our current techniques are already costly and slow and yet scale by some power law as the gate count increases. An analysis of the strategies open to us leads to the possibility that in many cases specialised DA hardware is cost effective. This paper then describes a series of trials to employ a 64 x 64 distributed array processor at DA tasks. Some unexpected results were obtained as algorithms evolved in the area of tracking, simulation, placement, test generation, fault simulation, and layout rule checking. The paper concludes with a discussion of the overheads incurred in employing unconventional hardware. |
| Starting Page | 339 |
| Ending Page | 344 |
| File Size | 478463 |
| Page Count | 6 |
| File Format | |
| ISBN | 0897910206 |
| ISSN | 01467123 |
| DOI | 10.1109/DAC.1982.1585521 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1982-06-14 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Very large scale integration Hardware Circuit faults Wiring Capacitance Wires Routing Circuit testing Cost function Partitioning algorithms |
| Content Type | Text |
| Resource Type | Article |
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