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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Nham, H.N. Bose, A.K. |
| Copyright Year | 1980 |
| Description | Author affiliation: Bell Laboratories, Murray Hill, NJ (Nham, H.N.) |
| Abstract | This paper describes a multiple delay simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. Integer rise and fall delays are associated with each transition and these delays are computed automatically based on device characteristics and circuit capacitances. The simulator has been extensively used for the design verification of production LSI chips. |
| Starting Page | 610 |
| Ending Page | 617 |
| File Size | 632225 |
| Page Count | 8 |
| File Format | |
| ISBN | 0897910206 |
| DOI | 10.1109/DAC.1980.1585310 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1980-06-23 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delay Circuit simulation Large scale integration Computational modeling Timing Logic devices MOSFETs Analytical models Costs Permission |
| Content Type | Text |
| Resource Type | Article |
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