NDLI: The Incorporation of Functional Level Element Routines into an Existing Digital Simulation System

Content Provider	IEEE Xplore Digital Library
Author	Thompson, E.W. Karger, P. Read, W.R. Ross, D. Smith, J. von Blucher, R.
Copyright Year	1980
Description	Author affiliation: Comprehensive Computing Systems and Services, Inc., Austin, TX (Thompson, E.W.)
Abstract	CC-TEGAS3 is a digital logic simulation system containing subsystems which can perform three different modes of simulation. These modes are used for logic or design verification, worst case timing analysis, and fault simulation. The basic device models are for Boolean gates, a wide range of flip-flops and latches, and a number of MOS elements such as transfer gates. A comprehensive list of functional level device models were incorporated into the system and the resulting system is called CC-TEGAS4. This approach was considered advantageous for today's technology, and an absolute necessity for the LSI and VLSI technologies that are forthcoming. This paper is concerned with the problems encountered and some of the techniques used to implement these functional level models, and results obtained in terms of reduction in required computer resources needed to simulate a network utilizing these new models.
Starting Page	394
Ending Page	401
File Size	852225
Page Count	8
File Format	PDF
ISBN	0897910206
DOI	10.1109/DAC.1980.1585277
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1980-06-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital simulation Logic devices Logic design Timing Analytical models Flip-flops Large scale integration Very large scale integration Computer networks Computational modeling
Content Type	Text
Resource Type	Article

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