NDLI: System level leakage reduction considering the interdependence of temperature and leakage

Content Provider	IEEE Xplore Digital Library
Author	Lei He Weiping Liao Stan, M.R.
Copyright Year	2004
Description	Author affiliation: University of California, Los Angeles (Lei He)
Abstract	The high leakage devices in nanometer technologies as well as the low activity rates in system-on-a-chip (SOC) contribute to the growing significance of leakage power at the system level. We first present system-level leakage-power modeling and characteristics and discuss ways to reduce leakage for caches. Considering the interdependence between leakage power and temperature, we then discuss thermal runaway and dynamic power and thermal management (DPTM) to reduce power and prevent thermal violations. We show that a thermal-independent leakage model may hide actual failures of DPTM. Finally, we present voltage scaling considering DPTM for different packaging options. We show that the optimal Vdd for the hest throughput may be smaller than the largest Vdd allowed by the given packaging platform, and that advanced cooling techniques can improve throughput significantly.
Starting Page	12
Ending Page	17
File Size	460641
Page Count	6
File Format	PDF
ISBN	1511838288
ISSN	0738100X
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-07-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Temperature Thermal management Power system modeling Microarchitecture Energy management Nanoscale devices System-on-a-chip Power system management Dynamic voltage scaling Integrated circuit packaging
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Power-thermal modeling and management of integrated circuits and systems.

System Level Leakage Reduction Considering The Interdependence Of Temperature And Leakage

System level leakage reduction considering the interdependence of temperature and leakage (2004).

2.3 System Level Leakage Reduction Considering the Interdependence of Temperature and Leakage ∗

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2.3 system level leakage reduction considering the interdependence of temperature and leakage ∗.

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