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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Cabodi, G. Camurati, P. Corno, F. Prinetto, P. Sonza Reorda, M. |
| Copyright Year | 1992 |
| Description | Author affiliation: Dipartimento di Autom. e Inf., Politecnico di Torino, Italy (Cabodi, G.; Camurati, P.; Corno, F.; Prinetto, P.; Sonza Reorda, M.) |
| Abstract | The authors present a technique for assessing the diagnostic power of an existing detection-oriented test pattern by means of diagnostic fault simulation and a procedure to improve it. The procedure successfully exploits enhanced symbolic finite state machine (FSM) equivalence proof algorithms. In order to resort to product machine traversal only when needed, special checks are performed to verify combinational identity and identity on reachable states. As all faults are attributed to their equivalence class, this method may be used to build a complete and exact diagnostic tree. Experimental results support the claim that the diagnosis of real-world synchronous sequential circuits has become feasible for the first time.< |
| Starting Page | 306 |
| Ending Page | 311 |
| File Size | 425150 |
| Page Count | 6 |
| File Format | |
| ISBN | 0818627808 |
| DOI | 10.1109/EURDAC.1992.246227 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1992-09-07 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Sequential diagnosis Circuit faults Circuit testing Fault diagnosis Sequential circuits Dictionaries Combinational circuits Flip-flops Clocks Fault detection |
| Content Type | Text |
| Resource Type | Article |
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