NDLI: Exploiting power-up delay for sequential optimization

Content Provider	IEEE Xplore Digital Library
Author	Singhal, V. Pixley, C. Aziz, A. Brayton, R.K.
Copyright Year	1995
Description	Author affiliation: Cadence Berkeley Labs., Berkeley, CA, USA (Singhal, V.)
Abstract	Recent work has identified the notion of safe replacement for sequential synchronous designs that may not have reset hardware or even explicitly known initial states. Safe replacement requires that a replacement design be indistinguishable from the original from the very first clock cycle after power-up. However, in almost any realistic application, the design is allowed to stabilize for many clock cycles before it is used. In this paper, we investigate the safety of a replacement if the replacement design is allowed to be clocked some cycles (that is, delayed) with arbitrary inputs before the design is reset. Having argued the safety of delay replacements, we investigate a new method of sequential optimization based upon the notion. We present experimental results to demonstrate that significant area optimizations can be gained by using this new notion of delay replaceability, and that there is a trade-off between the allowed number of clock cycles after power-up and the amount of optimization that can be obtained.
Starting Page	54
Ending Page	59
File Size	777444
Page Count	6
File Format	PDF
ISBN	0818671564
DOI	10.1109/EURDAC.1995.527389
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-09-18
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Clocks Design optimization Synchronization Hardware Safety Optimization methods Sequential circuits Latches Flip-flops
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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