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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shi, C.-J.R. |
| Copyright Year | 1996 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA (Shi, C.-J.R.) |
| Abstract | Via minimization is an important problem in integrated circuit layout and printed circuit board design. A linear (non-integral) programming approach to two-layer constrained via minimization (CVM) is presented. The approach finds optimum solutions for routings containing no more than three way splits, and guarantees provably good results for the general case. Most importantly, the size of linear programming formulation is polynomial in terms of the size of the CVM problem. The significance of the work lies in three aspects. First, since linear programming can be solved in polynomial time, the work thus provides, for the first time, a mathematical programming solution with computational efficiency comparable to known combinatorial CVM algorithms. Second, the compact linear programming approach is provably good and natural for general CVM, while previous restricted CVM algorithms are difficult to he extended to the general case. Third, the approach can handle additional constraints in a unified manner, and thus provides an efficient method for performance-driven layer assignment. The approach is based on some new graph-theoretic and polyhedron-combinatorial results presented on the structure of the CVM problem. |
| Starting Page | 635 |
| Ending Page | 640 |
| File Size | 636023 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780336623 |
| DOI | 10.1109/ASPDAC.1997.600347 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1997-01-28 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Linear programming Routing Wire Minimization Printed circuits Polynomials Cities and towns Integrated circuit layout Computational efficiency Transmission line theory |
| Content Type | Text |
| Resource Type | Article |
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