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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Stoffel, D. Kunz, W. Gerber, S. |
| Copyright Year | 1996 |
| Description | Author affiliation: Potsdam Univ., Germany (Stoffel, D.) |
| Abstract | This paper presents a technique to determine prime implicants in multi-level combinational networks. The method is based on a graph representation of Boolean functions called AND/OR reasoning graphs. This representation follows from a search strategy to solve the satisfiability problem that is radically different from conventional search for this purpose (such as exhaustive simulation, backtracking, BDDs). The paper shows how to build AND/OR reasoning graphs for arbitrary combinational circuits and proves basic theoretical properties of the graphs. It will be demonstrated that AND/OR reasoning graphs allow us to naturally extend basic notions of two-level switching circuit theory to multi-level circuits. In particular, the notions of prime implicants and permissible prime implicants are defined for multi-level circuits and it is proved that AND/OR reasoning graphs represent all these implicants. Experimental results are shown for PLA factorization. |
| Starting Page | 529 |
| Ending Page | 538 |
| File Size | 1083256 |
| Page Count | 10 |
| File Format | |
| ISBN | 0780336623 |
| DOI | 10.1109/ASPDAC.1997.600326 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1997-01-28 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Intelligent networks Boolean functions Data structures Tree graphs Decision trees Circuit simulation Switching circuits Fault tolerance Computer networks Combinational circuits |
| Content Type | Text |
| Resource Type | Article |
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