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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Arlat, Jean Constantinescu, Cristian Karlsson, Johan Nanya, Takashi Wood, Alan |
| Copyright Year | 2011 |
| Description | Author affiliation: Oracle, 501 Island Parkway, Belmont, CA 94002 - USA (Wood, Alan) || Canon Inc., 3-30-2 Shimomaruko, Ohta-ku, Tokyo 146-8501 - Japan (Nanya, Takashi) || AMD, 2950 E Harmony Rd., Fort Collins, CO 80528 - USA (Constantinescu, Cristian) || Dept. of Computer Science & Eng., Chalmers University of Technology, 41296 Göteborg - Sweden (Karlsson, Johan) || LAAS-CNRS and Université de Toulouse, 7, Av. du Colonel Roche 31077 - France (Arlat, Jean) |
| Abstract | Nanocomputing and related-enabling technologies hold the promise of higher performance and lower power consumption, as well as increased communication capabilities and functionality. In addition to the impact on today computerized systems, nanocomputing is an essential lever to foster the emerging cyberphysical system paradigm. However, the dependability and security of these unprecedentedly small devices, of their deployment, and of their interconnection remain uncertain. The main sources of concern are: • Nanometer devices are expected to be highly sensitive to process variations. The guard-bands used today for avoiding the impact of such variations will not represent a feasible solution in the future. As a consequence, timing errors and their higher frequency of occurrence have to be addressed. • New and intricate failure modes, specific to new materials, are expected to raise serious challenges to the design and test engineers. • Environment induced errors, such as single event upsets (SEU), are likely to occur more frequently than in the case of more conventional semiconductor devices. • Design of hardware architectures encompassing resilience techniques are needed to achieve the development of highly reliable energy efficient systems. • The increased complexity of the systems based on nanotechnology will require improved computer aided design (CAD) tools, as well as better validation techniques. • The security of nanocomputing systems may be threatened by malicious attacks targeting new vulnerable areas in the hardware. |
| Starting Page | 588 |
| Ending Page | 589 |
| File Size | 943115 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781424492329 |
| ISSN | 15300889 |
| e-ISBN | 9781424492336 |
| e-ISBN | 9781424492312 |
| DOI | 10.1109/DSN.2011.5958235 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-06-27 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Conferences Hardware Testing Computer architecture Program processors Materials |
| Content Type | Text |
| Resource Type | Article |
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