NDLI: Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits

Content Provider	IEEE Xplore Digital Library
Author	Shyue-Kung Lu Ting-Yu Chen Wei-Yuan Liu
Copyright Year	2006
Description	Author affiliation: Dept. of Electron. Eng., Fu-Jen Catholic Univ., Taipei (Shyue-Kung Lu; Ting-Yu Chen; Wei-Yuan Liu)
Abstract	Owing to the rapid advance in semiconductor fabrication technology, a large number of transistors can be incorporated onto a single chip. However, this will reduce the controllability and observability of the chip significantly. Consequently, testing such highly complex and dense circuits becomes very difficult and expensive. Therefore, we propose an efficient design-for-testability technique based on M-testability conditions for the 2D systolic DCT/IDCT processors in this paper. The cell fault model is adopted. For chip testing consideration, we modify the processing elements of the 2D array and make the module function bijective. The proposed DFT technique is also suitable for BIST implementation. The test pattern generator is simply a binary counter. Moreover, the adders and registers in each processing element can be combined as signature analyzers to perform accumulation and compression operations to evaluate the signatures during different test sessions. The signatures for each test session are stored in each processing element and propagated to the primary outputs when the test session is finished. An experimental chip is designed and implemented with Synopsys synthesis tools. Experimental results show that the hardware overhead of the BIST architecture for 2D DCT/IDCT architectures is less than 10%. The fault coverage of each processing element can achieve 98.18%
Sponsorship	IEEE Comput. Soc. TC on Fault-Tolerant Comput. Univ. of California, Riverside
Starting Page	97
Ending Page	104
File Size	949450
Page Count	8
File Format	PDF
ISBN	0769527248
DOI	10.1109/PRDC.2006.31
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Video coding Discrete cosine transforms Circuit testing Circuit faults Fabrication Transistors Controllability Observability Design for testability
Content Type	Text
Resource Type	Article

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