NDLI: SmartInjector: Exploiting intelligent fault injection for SDC rate analysis

Content Provider	IEEE Xplore Digital Library
Author	Jianli Li Qingping Tan
Copyright Year	2013
Description	Author affiliation: Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China (Jianli Li; Qingping Tan)
Abstract	Recently, researchers have shown that exploiting symptom-based solutions provides a promising way to achieve low-cost fault tolerance. However, these solutions cannot provide enough reliability due to lack of ability to handle silent data corruptions (SDCs). To address SDCs efficiently, it is important to identify them effectively. This paper presents an intelligent fault injection framework, SmartInjector, which can analyze the SDC rates of the instructions in an application accurately with affordable fault simulation efforts. Based on program analysis, SmartInjector firstly prunes the faults whose outcome can be known without fault simulation or the faults which are considered to be equivalent to other faults. SmartInjector also employs the fault outcome prediction technique to reduce the time for a single fault simulation. The decreased requirement of computational resources allows SmartInjector to perform detailed fault injection experiments to analyze SDC rate for each instruction in an application. Validation results show that the fault simulation time needed by SmartInjector is only about 0.15% of the time required for simulating all possible faults, while the analysis accuracy of SDC rate reaches to 94% on average. Unlike existing fault injection frameworks, SmartInjector is the first to exploit fault outcome prediction to reduce the single simulation time.
Sponsorship	IEEE Comput. Soc.
Starting Page	236
Ending Page	242
File Size	165096
Page Count	7
File Format	PDF
ISSN	15505774
e-ISBN	9781479915859
DOI	10.1109/DFT.2013.6653612
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Predictive models Registers Computational modeling Fault tolerance Fault tolerant systems Analytical models Transient analysis Fault outcome prediction Transient faults Program analysis Fault injection
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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