NDLI: Recent advances in stress and activation engineering for high-performance logic transistors

Content Provider	IEEE Xplore Digital Library
Author	Feudel, Thomas Horstmann, Manfred
Copyright Year	2008
Description	Author affiliation: AMD Saxony LLC & Co. KG, Wilschdorfer Landstrasse 101, D-01109 Dresden, Germany (Feudel, Thomas; Horstmann, Manfred)
Abstract	SOI technology is leading edge for high performance microprocessors. Performance per Watt is key and multiple core devices and their improved functionality are required to keep power comsumption low. AMD runs a unique transistor node to node progression model which devlivers at all times top notch performance from technology and lowers risk when moving to next technology generation. AMD gained leadership on strained Si and multi stressor integration. In a very mature state already DSL, SMT and SiGe. Besides stressors, advanced anneal is important to reduce diffusion and asymmetric device will help transistor performance. Reduction of parametric scattering is especially important for 45nm/32nm technology nodes. A special in-die measurement method has been developed to assess scattering in a thorough statistical way. Existing stressors like DSL, SMT, SiGe fully scale to 45nm pitches. HK/MG materials are the key for 32nm to keep GOX leakage under control and to allow gate scaling again.
Starting Page	1
Ending Page	34
File Size	189525757
Page Count	34
File Format	PDF
ISBN	9781424419500
DOI	10.1109/RTP.2008.4690535
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress Transistors DSL Surface-mount technology Silicon germanium Germanium silicon alloys Scattering Power engineering and energy Logic devices Microprocessors
Content Type	Text
Resource Type	Article

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