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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gerharz, J.C. Moers, J. Mussler, G. Grutzmacher, D. |
| Copyright Year | 2012 |
| Description | Author affiliation: Peter Grünberg Institut PGI 9, Institute for Semiconductor Nanoelectronics, Forschungszentrum Jülich, 52425. Germany (Gerharz, J.C.; Moers, J.; Mussler, G.; Grutzmacher, D.) |
| Abstract | In the d-DotFET device the strain introduced into a silicon capping layer grown on top of an ordered array of Ge islands is used. To achieve ordering and prevent randomly distribution of the Ge islands during epitaxial growth of Ge on silicon, template assisted self organization is utilized: the Si substrate is patterend by E-Beam lithography and subsequent reactive ion etching. During epitaxial growth by MBE the Ge islands grow in the predefined holes only, thus the position of the dots can be determined with a lateral accuracy of ±5 nm. This allows the alignment of the active device area to individual dots, thus utilizing the locally strained silicon layer. For MOSFETs were the dot will be preserved in the device, mobility enhancement of 22.5% can be achieved [1,2], while removing the dot leads to an mobility enhancement of 35%. |
| Starting Page | 139 |
| Ending Page | 142 |
| File Size | 197313 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467311977 |
| e-ISBN | 9781467311984 |
| DOI | 10.1109/ASDAM.2012.6418228 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-11-11 |
| Publisher Place | Slovakia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Silicon Etching Strain Transistors Lithography |
| Content Type | Text |
| Resource Type | Article |
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