NDLI: Combined DRAM and logic chip for massively parallel systems

Content Provider	IEEE Xplore Digital Library
Author	Kogge, P.M. Sunaga, T. Miyataka, H. Kitamura, K. Retter, E.
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA (Kogge, P.M.; Sunaga, T.; Miyataka, H.; Kitamura, K.)
Abstract	A new 5 V 0.8 /spl mu/m CMOS technology merges 100 K custom circuits and 4.5 Mb DRAM onto a single die that supports both high density memory and significant computing logic. One of the first chips built with this technology implements a unique Processor-In-Memory (PIM) computer architecture termed EXECUBE and has 8 separate 25 MHz CPU macros and 16 separate 32 K/spl times/9 b DRAM macros on a single die. These macros are organized together to provide a single part type for scaleable massively parallel processing applications, particularly embedded ones where minimal glue logic is desired. Each chip delivers 50 Mips of performance at 2.7 W. This paper overviews the basic chip technology and organization some projections on the future of EXECUBE-like PIM chips, and finally some lessons to be learned as to why this technology should radically affect the way we ought think about computer architecture.
Starting Page	4
Ending Page	16
File Size	878965
Page Count	13
File Format	PDF
ISBN	0818670749
DOI	10.1109/ARVLSI.1995.515607
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-03-27
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bandwidth CMOS logic circuits Central Processing Unit Computer architecture Costs CMOS technology Random access memory Concurrent computing Application software Logic devices
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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