NDLI: Silicon VLSI processing architectures incorporating integrated optoelectronic devices

Content Provider	IEEE Xplore Digital Library
Author	Cat, H.H. Lee, M. Buchanan, B. Wills, D.S. Brooke, M. Jokerst, N.M.
Copyright Year	1995
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Cat, H.H.; Lee, M.; Buchanan, B.; Wills, D.S.; Brooke, M.; Jokerst, N.M.)
Abstract	Integrated optoelectronic interconnects offer a potentially lower cost, higher density alternative to wire-based technologies for I/O and inter-chip communication. This paper outlines two systems being designed at Georgia Tech which incorporate integrated thin film optoelectronic devices onto high throughput VLSI digital processors. The first system places an array of thin film detectors on top of SIMD processing elements allowing direct area connections between sensors and processors. This allows extremely fast frame processing rates (1-10 thousand frames per second) which are required in high speed and scanned imaging systems. The second system presented incorporates inter-chip IR optoelectronic channels which pass transparently through silicon. These links allow communication between three dimensionally stacked chips supporting high throughput interconnect topologies. This paper demonstrates the potential of optoelectronic integrated VLSI systems for providing extremely dense and lightweight solutions in applications such as image processing.
Starting Page	17
Ending Page	27
File Size	623965
Page Count	11
File Format	PDF
ISBN	0818670749
DOI	10.1109/ARVLSI.1995.515608
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-03-27
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Very large scale integration Sensor arrays Throughput Thin film sensors Integrated optoelectronics Costs Thin film devices Optoelectronic devices Detectors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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