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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xin Fan Schrape, O. Marinkovic, M. Dahnert, P. Krstic, M. Grass, E. |
| Copyright Year | 2013 |
| Description | Author affiliation: IHP, Frankfurt (Oder), Germany (Xin Fan; Schrape, O.; Marinkovic, M.; Dahnert, P.; Krstic, M.; Grass, E.) |
| Abstract | Digital circuits often suffer from the switching noise when synchronized by a global clock. This work investigates the spectral peak attenuation of the switching current by applying Globally Asynchronous Locally Synchronous (GALS) design. It is theoretically proven that, in particular for a plesiochronous design with M clock domains, an attenuation of up to 20logM dB can be achieved at lower order harmonics of the clock frequency. Power-consumption balanced GALS partitioning is found to be preferred for spectral noise attenuation, since it provides robustness against the current shape variations in individual blocks. Experiments on a 130-nm CMOS synchronous/GALS dual-core FMCW-RADAR chip, named Lighthouse, have been performed. Comparing with the synchronous design, on the on-chip power supply, a spectral peak attenuation of 12.29 dB at the fundamental clock frequency can be measured for the power balanced GALS design with five plesio-chronous clocks. |
| Starting Page | 83 |
| Ending Page | 90 |
| File Size | 1063388 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781467359566 |
| ISSN | 15228681 |
| DOI | 10.1109/ASYNC.2013.28 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-05-19 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | FFT GALS SSN EMC |
| Content Type | Text |
| Resource Type | Article |
| Subject | Engineering |
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