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  1. International Symposium on Advanced Research in Asynchronous Circuits and Systems.
  2. Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings.
  3. On the existence of hazard-free multi-level logic
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2015 21st IEEE International Symposium on Asynchronous Circuits and Systems
2014 20th IEEE International Symposium on Asynchronous Circuits and Systems
2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems
2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems
2011 17th IEEE International Symposium on Asynchronous Circuits and Systems
2010 IEEE Symposium on Asynchronous Circuits and Systems
2009 15th IEEE Symposium on Asynchronous Circuits and Systems
2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)
12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)
11th IEEE International Symposium on Asynchronous Circuits and Systems
10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings.
Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings.
Proceedings Ninth International Symposium on Asynchronous Circuits and Systems
A coarse-grain phased logic CPU
The Lutonium: a sub-nanojoule asynchronous 8051 microcontroller
SNAP: a Sensor-Network Asynchronous Processor
Congestion and starvation detection in ripple FIFOs
Adaptive pipeline structures for speculation control
Energy and performance models for clocked and asynchronous communication
Timing measurements of synchronization circuits
Efficient self-timed interfaces for crossing clock domains
Fourteen ways to fool your synchronizer
Monotonic circuits with complete acknowledgement
On the existence of hazard-free multi-level logic
An analysis of determinacy using a trace-theoretic model of asynchronous circuits
Delay-insensitive, point-to-point interconnect using m-of-n codes
Self-timed ring for globally-asynchronous locally-synchronous systems
A high-speed clockless serial link transceiver
Low-latency control structures with slack
Asynchronous DRAM design and synthesis
Control signal sharing using data-path delay information at control data flow graph descriptions
A new class of asynchronous A/D converters based on time quantization
An investigation into the security of self-timed circuits
Asynchronous datapath with software-controlled on-chip adaptive voltage scaling for multirate signal processing applications
Author index
Proceedings Eighth International Symposium on Asynchronous Circuits and Systems
Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001
Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems
Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems
Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems
Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems
Proceedings Second Working Conference on Asynchronous Design Methodologies
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems

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Article

On the existence of hazard-free multi-level logic

Content Provider IEEE Xplore Digital Library
Author Nowick, S.M. O'Donnell, C.W.
Copyright Year 2003
Description Author affiliation: Dept. of Comput. Sci., Columbia Univ., New York, NY, USA (Nowick, S.M.; O'Donnell, C.W.)
Abstract This paper introduces a new method which, given an arbitrary Boolean function and specified set of (function hazard-free) input transitions, determines if any hazard free multilevel logic implementation exists. The algorithm is based on iterative decomposition, using disjunction and inversion. Earlier approaches by Nowick and Dill (1995) and Theobald and Nowick (1998) have been proposed to determine if a hazard free two-level logic implementation exists. However, it is well-known that the effects of multi-level transformations are quite complex: since they can both decrease and increase logic hazards in a given circuit. In this paper, a method is proposed to solve the hazard free multi-level existence problem. The method is proven to be both sound and complete for a large class of multi-level implementations. A novel contribution is to show that, if any hazard free multi-level solution exists, then a hazard free solution always exists using only 3 logic levels, in a 3-level NAND or OR-AND-OR structure. Moreover, in this case, it is shown there always exists a unique canonical hazard free 3-level implementation.
Sponsorship IEEE Comput. Soc. Tech. Committee on VLSI
Starting Page 109
Ending Page 120
File Size 456911
Page Count 12
File Format PDF
ISBN 0769518982
ISSN 15228681
DOI 10.1109/ASYNC.2003.1199171
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2003-05-12
Publisher Place Canada
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Hazards Boolean functions Asynchronous circuits Permission USA Councils Logic design Advertising IEEE services Telephony Computer science
Content Type Text
Resource Type Article
Subject Engineering
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