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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kondratyev, A. Sorensen, L. Streich, A. |
| Copyright Year | 2002 |
| Description | Author affiliation: Cadence Berkeley Lab., CA, USA (Kondratyev, A.) |
| Abstract | The roadblock to wide acceptance of asynchronous methodology is poor CAD support. Current asynchronous design tools require a significant re-education of designers, and their capabilities are far behind synchronous commercial tools. This paper considers the testing methodology for a particular subclass of asynchronous circuits (Null Convention Logic or NCL) that entirely relies on conventional CAD tools available at today's market. It is shown that for acyclic NCL pipelines a test pattern generation for stuck-at faults could be effectively solved through the construction and checking of the synchronous circuit with a set of faults "equivalent" to the original NCL circuit. This result is extended to arbitrary NCL structures by applying the partial scan technique to break computational loops. The method guarantees 100% stuck-at fault coverage in NCL systems, which is confirmed by experimental data. |
| Sponsorship | IEEE Comput. Soc. Tech. Committee on VLSI |
| Starting Page | 171 |
| Ending Page | 180 |
| File Size | 400456 |
| Page Count | 10 |
| File Format | |
| ISBN | 0769515401 |
| ISSN | 15228681 |
| DOI | 10.1109/ASYNC.2002.1000307 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-04-08 |
| Publisher Place | UK |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuit testing Asynchronous circuits Circuit faults Logic design Design automation Circuit synthesis Logic testing Logic circuits Circuit simulation Laboratories |
| Content Type | Text |
| Resource Type | Article |
| Subject | Engineering |
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