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  1. International Symposium on Advanced Research in Asynchronous Circuits and Systems.
  2. Proceedings Eighth International Symposium on Asynchronous Circuits and Systems
  3. Synchronous interlocked pipelines
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2015 21st IEEE International Symposium on Asynchronous Circuits and Systems
2014 20th IEEE International Symposium on Asynchronous Circuits and Systems
2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems
2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems
2011 17th IEEE International Symposium on Asynchronous Circuits and Systems
2010 IEEE Symposium on Asynchronous Circuits and Systems
2009 15th IEEE Symposium on Asynchronous Circuits and Systems
2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)
12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)
11th IEEE International Symposium on Asynchronous Circuits and Systems
10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings.
Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings.
Proceedings Eighth International Symposium on Asynchronous Circuits and Systems
Proceedings Eighth International Symposium on Asynchronous Circuits and Systems
Synchronous interlocked pipelines
High-speed QDI asynchronous pipelines
Energy-efficient pipelines
A negative-overhead, self-timed pipeline
An event spacing experiment
Clock synchronization through handshake signalling
Point to point GALS interconnect
A dual-mode synchronous/asynchronous CORDIC processor
An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 GigaHertz
Probabilistic timing analysis of asynchronous systems with moments of delays
Generation and verification of timing constraints for fine-grain pipelined asynchronous data-path circuits
Relative timing based verification of timed circuits and systems
Asynchronous circuit synthesis by direct mapping: interfacing to environment
Design and performance analysis of buffers: a constructive approach
Checking delay-insensitivity: 10/sup 4/ gates and beyond
Adding synchronous and LSSD modes to asynchronous circuits
Testing of asynchronous designs by "inappropriate" means. Synchronous approach
A functional test methodology for globally-asynchronous locally-synchronous systems
On-chip structures for timing measurement and test
SPA - a synthesisable Amulet core for smartcard applications
Improving smart card security using self-timed circuits
Author index
Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001
Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems
Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems
Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems
Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems
Proceedings Second Working Conference on Asynchronous Design Methodologies
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems

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Synchronous interlocked pipelines

Content Provider IEEE Xplore Digital Library
Author Jacobson, H.M. Kudva, P.N. Bose, P. Cook, P.W. Schuster, S.E. Mercer, E.G. Myers, C.J.
Copyright Year 2002
Description Author affiliation: Design Autom. Dept., IBM Thomas J. Watson Res. Center, NY, USA (Jacobson, H.M.; Kudva, P.N.)
Abstract Locality principles are becoming paramount in controlling advancement of data through pipelined systems. Achieving fine grained power down and progressive pipeline stalls at the local stage level is therefore becoming increasingly, important to enable lower dynamic power consumption while keeping introduced switching noise under control as well as avoiding global distribution of timing critical stall signals. It has long been known that the interlocking properties of as asynchronous pipelined systems have a potential to provide such benefits. However it has not been understood how such interlocking can be achieved in synchronous pipelines. This paper presents a novel technique based on local clock gating and synchronous handshake protocols that achieves stage level interlocking characteristics in synchronous pipelines similar to that of asynchronous pipelines. The presented technique is directly applicable to traditional synchronous pipelines and works equally well for two-phase clocked pipelines based on transparent latches, as well as one-phase clocked pipelines based on master-slave latches.
Sponsorship IEEE Comput. Soc. Tech. Committee on VLSI
Starting Page 3
Ending Page 12
File Size 325279
Page Count 10
File Format PDF
ISBN 0769515401
ISSN 15228681
DOI 10.1109/ASYNC.2002.1000291
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2002-04-08
Publisher Place UK
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Pipelines Clocks Latches Power dissipation Control systems Energy consumption Integrated circuit noise Jacobian matrices Design automation Circuit noise
Content Type Text
Resource Type Article
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