NDLI: Material challenges for wafer level packaging

Content Provider	IEEE Xplore Digital Library
Author	Ma, B. Zhang, E. Sun Hee Hong Tong, Q. Savoca, A.
Copyright Year	2000
Description	Author affiliation: Nat. Starch & Chem. Co., Bridgewater, NJ, USA (Ma, B.)
Abstract	Flip chip as the smallest packaging design has been used in more and more electronic applications. Flip chip underfill is an essential component for the reliability of the package. Currently, the dispensing process is done on each individual chip level after the solder interconnects have been made. The device then has to go through a separate curing process to harden the underfill material. The current underfilling process is cumbersome and is one of the cost drivers of flip chip application. In wafer level flip chip packaging, the dispensing is made over the whole wafer in one step. After dicing, the reflow and the curing of underfill will be accomplished also in one step. The saving on process cost will be substantial. The new process brings new challenges to underfill material development. In addition to performing the reinforcement role as an underfill, these new materials have to be compatible with the proposed wafer level process. In addition, the underfill material has to act as a fluxing agent during solder reflow. The underfill materials also have to demonstrate good room temperature stability after being dispensed onto wafer, handled at ambient environment, and before being cured in the reflow oven. The authors will discuss the parameters that determine the material performance at each processing step as well as the material development effort in a wafer-level underfill development program, which is sponsored by the Advanced Technology Program (ATP).
Starting Page	68
Ending Page	73
File Size	424366
Page Count	6
File Format	PDF
ISBN	0930815599
DOI	10.1109/ISAPM.2000.869245
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-08-08
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer scale integration Flip chip Curing Costs Semiconductor materials Electronics packaging Temperature Sun Chemicals Stability
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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