NDLI: Reducing dTLB energy through dynamic resizing

Content Provider	IEEE Xplore Digital Library
Author	Delaluz, V. Kandemir, M. Sivasubramaniam, A. Irwin, M.J. Vijaykrishnan, N.
Copyright Year	2003
Description	Author affiliation: Pennsylvania State Univ., University Park, PA, USA (Delaluz, V.; Kandemir, M.; Sivasubramaniam, A.; Irwin, M.J.; Vijaykrishnan, N.)
Abstract	Translation look-aside buffer (TLB), which is small content addressable memory (CAM) structure used to translate virtual addresses to physical addresses, can consume significant energy in some architectures. In addition, its power density is high, due to its small area. Consequently, reducing power consumption of TLB is important for both high-end and low-end systems. While a large TLB might be preferable from the performance angle, it can also lead to excessive dynamic energy consumption. We focus on data TLB (dTLB), and propose an architectural solution to this problem which is based on dynamically resizing the dTLB considering application execution behavior. Our objective is to give the application the minimum dTLB size (at any point) without significantly degrading its performance. We present two different implementations of this idea, and give experimental data demonstrating that it is very effective in practice.
Sponsorship	IEEE Comput. Soc. IEEE Circuits & Syst. Soc. IEEE Electron Devices Soc
Starting Page	358
Ending Page	363
File Size	490723
Page Count	6
File Format	PDF
ISBN	0769520251
ISSN	10636404
DOI	10.1109/ICCD.2003.1240919
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Computer aided manufacturing CADCAM Degradation Circuits Banking Associative memory Energy management Engineering profession Filter bank
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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