NDLI: Using offline and online BIST to improve system dependability

Content Provider	IEEE Xplore Digital Library
Author	Steininger, A. Vilanek, J.
Copyright Year	2002
Description	Author affiliation: Vienna Univ. of Technol., Austria (Steininger, A.; Vilanek, J.)
Abstract	Fault-tolerant distributed real-time systems are facing many new challenges. Although many techniques provide effective masking of node failures on the architectural level, several trends are aggravating the reliability demands on the node level. Starting with a brief presentation of the fault tolerance properties of the time-triggered architecture TTA the corresponding support by the time-triggered protocol controller (TTPC-C) is discussed. We propose a strategy for improving these properties with respect to the anticipated new fault scenarios. It turns out that the application of BIST during node startup and before node reintegration improves system fault tolerance. Additionally a combined strategy of online BIST and error correction can efficiently protect memory. We illustrate the implementation of the proposed mechanisms. Our implementation experiences on an FPGA platform show that the involved overheads are moderate.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Design Autom. IEEE Circuits & Syst. Soc
Starting Page	277
Ending Page	280
File Size	1997469
Page Count	4
File Format	PDF
ISBN	0769517005
ISSN	10636404
DOI	10.1109/ICCD.2002.1106782
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-18
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Computer architecture Fault tolerant systems Electromagnetic transients Fault detection Real time systems Automotive applications Packaging Electromagnetic interference Delay
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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