NDLI: Assignment-space exploration approach to concurrent data-path/floorplan synthesis

Content Provider	IEEE Xplore Digital Library
Author	Oohashi, K. Kaneko, M. Tayu, S.
Copyright Year	2000
Description	Author affiliation: Sch. of Inf. Sci., Japan Adv. Inst. of Sci. Technol., Japan (Oohashi, K.)
Abstract	As the geometrical design rules of VLSIs become finer into the order of deep sub-micron, the impact of wires to VLSI performance becomes larger relatively to the other components, and their estimation at RT-level description and performance-driven datapath synthesis need explicit connectivity information about RT-level architecture and its floorplan. In this paper, an assignment-driven approach to the datapath synthesis incorporated with one-dimensional floor planning is proposed. In our approach, scheduling and one-dimensional floorplanning, both of which are driven by iteratively generated functional unit and register assignment (binding), are performed fully concurrently. Pseudo-branch-and-bound assignment space exploration is adopted for generating assignments in this pilot system.
Starting Page	370
Ending Page	375
File Size	549400
Page Count	6
File Format	PDF
ISBN	0769508014
ISSN	10636404
DOI	10.1109/ICCD.2000.878310
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-09-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Scheduling Very large scale integration Wires Space exploration High level synthesis Clocks Delay Voltage Signal design Information science
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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