NDLI: DRAM-page based prediction and prefetching

Content Provider	IEEE Xplore Digital Library
Author	Haifeng Yu Kedem, G.
Copyright Year	2000
Description	Author affiliation: Dept. of Comput. Sci., Duke Univ., Durham, NC, USA (Haifeng Yu)
Abstract	This paper describes and evaluates DRAM-page based cache-line prediction and prefetching architecture. The scheme takes DRAM access timing into consideration in order to reduce prefetching overhead, amortizing the high cost of DRAM access by fetching two cache lines that reside on the same DRAM-page in a single access. On each DRAM access, one or two cache blocks may be prefetched. We combine three prediction mechanisms: history mechanism, stride, and one block lookahead, make them DRAM page sensitive and deploy them in an effective adaptive prefetching strategy. Our simulation shows that the prefetch mechanism can greatly improve system performance. Using a 32-KB prediction table cache, the prefetching scheme improves performance by 26%-55% on average over a baseline configuration, depending on the memory model. Moreover, the simulation shows that prefetching is more cost-effective than simply increasing L2-cache size or using a one block lookahead prefetching scheme. Simulation results also show that DRAM-page based prefetching yields higher relative performance as processors get faster, making the prefetching scheme more attractive for next generation processors.
Starting Page	267
Ending Page	275
File Size	857980
Page Count	9
File Format	PDF
ISBN	0769508014
ISSN	10636404
DOI	10.1109/ICCD.2000.878296
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-09-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Prefetching Random access memory Costs Delay Timing History System performance Computer science Computer architecture Magnetic heads
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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