NDLI: P6 Binary Floating-Point Unit

Content Provider	IEEE Xplore Digital Library
Author	Son Dao Trong Schmookler, M. Schwarz, E.M. Kroener, M.
Copyright Year	2007
Description	Author affiliation: IBM Server Div., Boeblingen (Son Dao Trong)
Abstract	The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a technology independent measure. For most dependent instructions, its fused multiply-add dataflow has only 6 effective pipeline stages. This is nearly equivalent to its predecessor, the Power 5, even though its technology independent frequency has increased over 70%. Overall the frequency has improved over 100%. It achieves this high performance through aggressive feedback paths, circuit design and layout. The pipeline has 7 stages but data may be fed back to dependent operations prior to rounding and complete normalization. Division and square root algorithms are also described which take advantage of high-precision linear approximation hardware for obtaining a reciprocal or reciprocal square root approximation.
Starting Page	77
Ending Page	86
File Size	242802
Page Count	10
File Format	PDF
ISBN	0769528546
ISSN	10636889
DOI	10.1109/ARITH.2007.26
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-25
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Frequency Yarn Testing Circuit synthesis Delay Time measurement Approximation algorithms Linear approximation Hardware data processing without stalls. Floating-point unit denormal result handling aggressive data forwarding high-frequency design
Content Type	Text
Resource Type	Article

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