NDLI: Impact of sharing-based thread placement on multithreaded architectures

Content Provider	IEEE Xplore Digital Library
Author	Thekkath, R. Eggers, S.J.
Copyright Year	1994
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA (Thekkath, R.; Eggers, S.J.)
Abstract	Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interference and degrade overall performance. One technique to reduce the interconnect traffic is to co-locate threads that share data on the same processor. Multiple threads sharing in the cache should reduce compulsory and invalidation misses, thereby improving execution rime. To test this hypothesis, the authors compared a variety of thread placement algorithms via trace-driven simulation of fourteen coarse- and medium-grain parallel applications on several multithreaded architectures. The results contradict the hypothesis. Rather than decreasing, compulsory and invalidation misses remained neatly constant across all placement algorithms, for all processor configurations, even with an infinite cache. That is, sharing-based-placement had no (positive) effect on execution time. Instead load balancing was the critical factor that affected performance. The results were due to one or both of the following reasons: (1) the sequential and uniform access of shared data by the application's threads and (2) the insignificant number of data references that require interconnect access, relative to the total number of instructions.<>
Starting Page	176
Ending Page	186
File Size	1221655
Page Count	11
File Format	PDF
ISBN	0818655100
DOI	10.1109/ISCA.1994.288151
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-18
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Yarn Computer architecture Switches Delay Degradation Testing Load management Computer science Processor scheduling Telecommunication traffic
Content Type	Text
Resource Type	Article

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