NDLI: Expected I-cache miss rates via the gap model

Content Provider	IEEE Xplore Digital Library
Author	Quong, R.W.
Copyright Year	1994
Description	Author affiliation: Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA (Quong, R.W.)
Abstract	To evaluate the performance of a memory system, computer architects must determine the miss rate m of a cache C when running program P. Typically, the measured miss rate depends on the specific address mapping M of P set arbitrarily by the compiler and linker. The author removes the effect of the address-mapping on the miss rate by analyzing a symbolic trace T of basic blocks. By assuming each basic block has an equal probability of ending up anywhere in the address map, he determines the expected miss rate averaged over all possible address mappings. The resulting gap model gives the expected miss rate for instruction caches of varying cache size, line size, and set associativity. The model is simple but robust, and turns out to be the familiar LRU stack model with a statistical viewpoint. The model allows a trace of arbitrary length to he compactly summarized in a few thousand bytes of information. It also predicts how an intervening trace, such as an operating system call or a task switch, will affect the miss rate. Comparisons to measured miss rates from SPEC 92 instruction traces show that the model typically has relative differences of less than 20% for a variety of cache parameters.<>
Starting Page	372
Ending Page	383
File Size	990957
Page Count	12
File Format	PDF
ISBN	0818655100
DOI	10.1109/ISCA.1994.288134
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-04-18
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Switches Electric variables measurement Robustness Predictive models Operating systems Time measurement Sun Computational modeling Benchmark testing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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