NDLI: Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches

Content Provider	IEEE Xplore Digital Library
Author	Chuanjun Zhang
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Sci. & Electr. Eng., Missouri Univ., Kansas, MO (Chuanjun Zhang)
Abstract	Level one cache normally resides on a processor's critical path, which determines the clock frequency. Direct-mapped caches exhibit fast access time but poor hit rates compared with same sized set-associative caches due to non-uniform accesses to the cache sets, which generate more conflict misses in some sets while other sets are underutilized. We propose a technique to reduce the miss rate of direct mapped caches through balancing the accesses to cache sets. We increase the decoder length and thus reduce the accesses to heavily used sets without dynamically detecting the cache set usage information. We introduce a replacement policy to direct-mapped cache design and increase the access to the underutilized cache sets with the help of programmable decoders. On average, the proposed balanced cache, or B-cache, achieves 64.5% and 37.8% miss rate reductions on all 26 SPEC2K benchmarks for the instruction and data caches, respectively. This translates into an average IPC improvement of 5.9%. The B-cache consumes 10.5% more power per access but exhibits 2% total memory access related energy saving due to the miss rate reductions and hence the reduction to applications' execution time. Compared with previous techniques that aim at reducing the miss rate of direct-mapped caches, our technique requires only one cycle to access all cache hits and has the same access time of a direct-mapped cache
Starting Page	155
Ending Page	166
File Size	391297
Page Count	12
File Format	PDF
ISBN	076952608X
ISSN	10636897
DOI	10.1109/ISCA.2006.12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Clocks Frequency Delay Computer science Cities and towns High performance computing Bridges Multiplexing History
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Balanced instruction cache: reducing conflict misses of direct-mapped caches through balanced subarray accesses

Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches

Balanced instruction cache: reducing conflict misses of direct- mapped caches through balanced subarray accesses.

Balanced instruction cache: Reducing conflict misses of direct-mapped caches through balanced subarray accesses (2005)

Balanced Cache:Reducing Conflict Misses of Direct-Mapped Caches

Separating conflict misses to reduce miss-rate of caches through an unified replacement policy

Reducing Conflict Misses in Caches (2003)

Avoiding conflict misses dynamically in large direct-mapped caches

Effective padding of multidimensional arrays to avoid cache conflict misses

Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches

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