NDLI: The BlackWidow High-Radix Clos Network

Content Provider	IEEE Xplore Digital Library
Author	Scott, S. Abts, D. Kim, J. Dally, W.J.
Copyright Year	2006
Description	Author affiliation: Cray Inc., Chippewa Falls, WI (Scott, S.; Abts, D.)
Abstract	This paper describes the radix-64 folded-Clos network of the Cray BlackWidow scalable vector multiprocessor. We describe the BlackWidow network which scales to 32Kprocessors with a worst-case diameter of seven hops, and the underlying high-radix router micro architecture and its implementation. By using a high-radix router with many narrow channels we are able to take advantage of the higher pin density and faster signaling rates available in modern ASIC technology. The BlackWidow router is an 800 MHz ASIC with 64 18.75Gb/s bidirectional ports for an aggregate off-chip bandwidth of 2.4Tb/s. Each port consists of three 6.25Gb/s differential signals in each direction. The router supports deterministic and adaptive packet routing with separate buffering for request and reply virtual channels. The router is organized hierarchically (Kim et al., 2005) as an 8times8 array of tiles which simplifies arbitration by avoiding long wires in the arbiters. Each tile of the array contains a router port, its associated buffering, and an 8times8 router subswitch. The router ASIC is implemented in a 90nm CMOS standard cell ASIC technology and went from concept to tapeout in 17 months
Starting Page	16
Ending Page	28
File Size	815140
Page Count	13
File Format	PDF
ISBN	076952608X
ISSN	10636897
DOI	10.1109/ISCA.2006.40
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network topology Application specific integrated circuits Bandwidth Delay Switches Multiprocessor interconnection networks Costs Microarchitecture Tiles Synchronization
Content Type	Text
Resource Type	Article

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