NDLI: The performance potential of multiple functional unit processors

Content Provider	IEEE Xplore Digital Library
Author	Pleszkun, A.R. Sohi, G.S.
Copyright Year	1988
Description	Author affiliation: Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA (Pleszkun, A.R.; Sohi, G.S.)
Abstract	The interaction is investigated of pipelining and multiple-functional units in single-processor machines, to gain an understanding of how each of these techniques contribute to performance improvement. A CRAY-like processor model is studied. The issue rate (instructions per clock cycle) is used as the performance measure. The base, nonpipelined, machine is then systematically augmented with more and more hardware features and the performance impact of each feature is evaluated. It is found that in nonvector machines, pipelining multiple-function units does not provide significant performance improvements. Dataflow limits are then derived for benchmark programs to determine the performance potential of each benchmark. In addition, other limits are computed which apply more realistic constraints on a computation. Based on these more realistic limits, it is determined to be worthwhile to investigate the performance improvements that can be achieved from issuing multiple instructions during each clock cycle. Several hardware approaches are evaluated for issuing multiple instructions each clock cycle.<>
Starting Page	37
Ending Page	44
File Size	892994
Page Count	8
File Format	PDF
ISBN	0818608617
DOI	10.1109/ISCA.1988.5208
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-05-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Pipeline processing Hardware Performance gain
Content Type	Text
Resource Type	Article

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