NDLI: Validating executable controller specifications through formal model checking

Content Provider	IEEE Xplore Digital Library
Author	Scillieri, J.J. Butts, K.R. Freudenberg, J.S.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA (Scillieri, J.J.)
Abstract	In many embedded control system applications, the control algorithm includes both logical and data flow portions. We apply formal methods of system verification to discrete-state algorithms. Specifically, we make use of a formal model checking tool to prove or disprove various properties of the algorithm. Questions pertaining to the achievability of states and paths and proper variable assignment are cast as logical assertions in computation tree logic (CTL), and evaluated using the model checker. In addition, we describe an approach for generating scenarios; that is, a sequence of inputs and parameters that will take a discrete-state system model through a given sequence. We present several examples illustrating various questions that the designer may wish to pose, and an appropriate CTL assertion for each.
Starting Page	179
Ending Page	184
File Size	545777
Page Count	6
File Format	PDF
ISBN	0780365666
DOI	10.1109/CACSD.2000.900208
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-09-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Mathematical model System testing Power system modeling Control system synthesis Logic Design engineering Computer science Mechanical power transmission Laboratories Application software
Content Type	Text
Resource Type	Article

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