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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Bufler, F.M. Aubry-Fortuna, V. Bournel, A. Braccioli, M. Dollfus, P. Esseni, D. Fiegna, C. Gamiz, F. De Michielis, M. Palestri, P. Saint-Martin, J. Sampedro, C. Sangiorgi, E. Selmi, L. Toniutti, P. |
| Copyright Year | 2010 |
| Description | Author affiliation: IIS, ETH Zurich, CH-8092 Zürich, Switzerland (Bufler, F.M.) || IEF, University Paris-Sud, CNRS, Orsay, France (Aubry-Fortuna, V.; Bournel, A.; Dollfus, P.; Saint-Martin, J.) || ARCES-DEIS, University of Bologna, Italy (Braccioli, M.; Fiegna, C.; Sangiorgi, E.) || DIEGM, Via delle Scienze 208, University of Udine, 33100 Udine, Italy (Esseni, D.; De Michielis, M.; Palestri, P.; Selmi, L.; Toniutti, P.) || Nanoelectronics Research Group, University of Granada, Spain (Gamiz, F.; Sampedro, C.) |
| Abstract | Long-channel effective mobilities as well as transfer characteristics of a 32 nm single-gate SOI and a 16 nm double-gate (DG) MOSFET have been simulated with live different Monte Carlo (MC) device simulators. The differences are mostly rather small for the SOI-FET with quantum effects having a minor effect on threshold voltage due to the lowly doped channel, while the two multi-subband MC simulators show some prominent deviations in the case of the DG-FET. High-K mobility degradation by remote phonon scattering (RPS) in free carrier MC approximation leads to smaller performance degradation compared to multi-subband MC with remote Coulomb scattering (RCS) and RPS, but requires further investigations. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 133024 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424493838 |
| e-ISBN | 9781424493845 |
| DOI | 10.1109/IWCE.2010.5677952 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-10-26 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Scattering Logic gates Monte Carlo methods Silicon Phonons MOSFET circuits Surface roughness |
| Content Type | Text |
| Resource Type | Article |
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