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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Okamoto, K. Miyata, M. Kishigami, H. Miyamori, T. Sato, T. |
| Copyright Year | 1988 |
| Description | Author affiliation: Toshiba Corp., Ibaraki, Japan (Okamoto, K.; Miyata, M.; Kishigami, H.; Miyamori, T.; Sato, T.) |
| Abstract | The architecture of the TX3 implementation of the TRON-CHIP32 specification is discussed. TX3 supports the full instruction set, including the decimal, floating-point, and other complex instructions. Average performance above 10-MIPS is expected. This performance level is obtained by the use of an 8-kB instruction cache, 8-kB data cache, decoded instruction loop buffer, three instruction execution units, and the ability to issue up to two instructions per cycle.< |
| Starting Page | 25 |
| Ending Page | 29 |
| File Size | 330693 |
| Page Count | 5 |
| File Format | |
| ISBN | 0818608285 |
| DOI | 10.1109/CMPCON.1988.4822 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1988-02-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Microprocessors Decoding Registers Operating systems Workstations Memory management Pipelines Semiconductor devices Laboratories User interfaces |
| Content Type | Text |
| Resource Type | Article |
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