NDLI: A high-speed, byte-serial, multiple-bus interconnection network

Content Provider	IEEE Xplore Digital Library
Author	Armstrong, W.J. Pohm, A.V. Davis, J.A.
Copyright Year	1989
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA (Armstrong, W.J.; Pohm, A.V.; Davis, J.A.)
Abstract	A research project at Iowa State University to investigate the use of a high-speed, byte-serial bus to implement a multiple-bus interconnection network for a fine-grain parallel architecture is discussed. The project focuses on the electrical properties of the bus, high-speed serial transmission, and bus contention resolution. Prototypes were developed to test critical aspects of the design, and the network was simulated to analyze its performance within the context of the parallel architecture. Results indicate that the network can effectively interconnect many processors (64) with relatively few buses (5), thereby giving a low packplane line count. By making a uniform bus that sent bytes at a rate limited only by clock skew, it was possible to increase the information transmission rate on a line by a factor of 4-10 over a conventional bus. This allowed for several high-speed buses with a limited pin count. It is concluded that multiple-bus networks offer the connectivity and bandwidth of a crossbar switch at a reasonable implementation cost.<>
Starting Page	64
Ending Page	69
File Size	531055
Page Count	6
File Format	PDF
DOI	10.1109/PACRIM.1989.48307
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-06-01
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiprocessor interconnection networks Parallel architectures Switches Virtual prototyping Testing Analytical models Context modeling Performance analysis Clocks Bandwidth
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An analytic model and optimal clustering for multiple-bus multiprocessor systems

k-ary n-trees: high performance networks for massively parallel architectures

Models for high-speed interconnection networks performance analysis

Performance model for a prioritized multiple-bus multiprocessor system

Performance analysis of multiprocessor architectures via analytical simulation

Multiple bus-based hierarchical multiprocessors and their bandwidth analysis

Queuing network modeling of a cluster-based parallel system

A partial-multiple-bus computer structure with improved cost-effectiveness

A comprehensive modeling for performance evaluation of regular interconnection network

A high-speed, byte-serial, multiple-bus interconnection network

Similar Documents

An analytic model and optimal clustering for multiple-bus multiprocessor systems

k-ary n-trees: high performance networks for massively parallel architectures

Models for high-speed interconnection networks performance analysis

Performance model for a prioritized multiple-bus multiprocessor system

Performance analysis of multiprocessor architectures via analytical simulation

Multiple bus-based hierarchical multiprocessors and their bandwidth analysis

Queuing network modeling of a cluster-based parallel system

A partial-multiple-bus computer structure with improved cost-effectiveness

A comprehensive modeling for performance evaluation of regular interconnection network

A high-speed, byte-serial, multiple-bus interconnection network