NDLI: Programming Heterogeneous Systems with Array Types

Content Provider	IEEE Xplore Digital Library
Author	Xiang Cui Xiaowen Li Yifeng Chen
Copyright Year	2015
Description	Author affiliation: HCST Key Lab., Peking Univ., Beijing, China (Xiang Cui; Yifeng Chen) \|\| Air Defense Forces Acad., Zhengzhou, China (Xiaowen Li)
Abstract	This paper describes the use of array notation called Parray in refinement of parallel programs concerning array type that separates the physical data layout and logical structure of multi-dimensional data, and the control flow diversion of heterogeneous processor units. A case study on matrix multiplication demonstrates refinement of Parray programs: the code evolves from a simple single CPU-thread code to a multi-thread code on CPU/MIC and then a GPU code by modifying the array types in only a few lines of code. A GPU-based SGEMM is implemented in Parray and achieves almost the same Gflops of CUBLAS 4.0 when testing on a single node of Tian-1A system. Because the code operates directly on the logical structure of array, the same SGEMM code can work on different physical array data layouts.
Starting Page	1067
Ending Page	1074
File Size	216190
Page Count	8
File Format	PDF
ISBN	9781479980062
DOI	10.1109/CCGrid.2015.113
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-04
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Arrays Graphics processing units Instruction sets Microwave integrated circuits Programming Process control Layout programming interface heterogeneous programming array type
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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