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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Inoue, K. Moshnyaga, V.G. Murakami, K. |
| Copyright Year | 2002 |
| Description | Author affiliation: Dept. of Electron. Eng.& Comput. Sci., Fukuoka Univ., Japan (Inoue, K.; Moshnyaga, V.G.) |
| Abstract | This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the switching activity of bit-lines. If a read bit-value indicates '0', the precharged bitline is discharged. In this scenario, a bit-line switching takes place and consumes power. Otherwise, the precharged bit-line level is maintained until the next access, thus no bit-line switching occurs. In our approach, the binary-patterns to be assigned to op-codes are determined based on the frequency of instructions for reducing the bit-line switching activity. Application programs are analyzed in advance, and then binary-patterns including many '1's' are assigned to the most frequently referenced instructions. In our evaluation, it is observed that the proposed approach can reduce bit-line switching by 40%. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 483266 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780376900 |
| DOI | 10.1109/APCCAS.2002.1115094 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-10-28 |
| Publisher Place | Indonesia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Energy consumption Read only memory Frequency Embedded system Voltage Random access memory Computer science Informatics Pattern analysis Batteries |
| Content Type | Text |
| Resource Type | Article |
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