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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hussein, A. Saleh, H. Mohammad, B. John, E. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Texas at San Antonio, San Antonio, TX (Hussein, A.) |
| Abstract | Active power, area, architecture, and timing constraints are the major factors in choosing SRAM-based memory organization in contemporary submicron SOCs. In this paper we add the effect of SRAM organization on leakage power as another major factor to consider in selecting a cache organization. Leakage power becomes an important factor for sub 100 nm process technology especially for SRAM-based memory because of the high percentage of ideal circuit to active circuit in any given time. We present the relationship between the SRAM organization and the leakage power at the following process nodes: 32 nm, 45 nm, 65 nm, 90 nm, 130 nm and 180 nm using the predictive technology models (PTM). SPICE simulations results of leakage power versus SRAM organization for a 1-kbits SRAM design is presented in details. |
| Starting Page | 775 |
| Ending Page | 778 |
| File Size | 602430 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424421664 |
| ISSN | 15483746 |
| DOI | 10.1109/MWSCAS.2008.4616914 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-08-10 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Leakage current Random access memory Transistors Organizations Simulation Integrated circuit modeling CMOS integrated circuits Leakage cache SRAM Memory |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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