NDLI: An enhanced fast encoding method for vector quantization by constructing new feature based on the variances of subvectors

Please wait, while we are loading the content...

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

2008 51st Midwest Symposium on Circuits and Systems

2007 50th Midwest Symposium on Circuits and Systems

2006 49th IEEE International Midwest Symposium on Circuits and Systems

48th Midwest Symposium on Circuits and Systems, 2005.

The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.

Volume 3 - 2004

Volume 2 - 2004

Volume 1 - 2004

The 2004 47th Midwest Symposium on Circuits and Systems

The 2004 47th Midwest Symposium on Circuits and Systems

Message from the MWSCAS 2004 General Chair

Message from the MWSCAS 2004 technical program chair

MWSCAS 2004 Technical Track Chairs

MWSCAS 2004 Steering Committee

MWSCAS 2004 Technical Reviewers

Chameleon: a dual-mode bluetooth/802.11b receiver

Complex signal processing is not-complex

In praise of Japanese engineering; In praise of Hiroshima

On the origins of DSP

Digital signal processing: road to the future

Future PDA terminals with a TOPS DSP

Conference rooms, registration and coffee break

MWSCAS 2004 conference schedule

Table of content

On the optimum design of gain-boosting amplifier for high-speed and low-voltage applications

Modeling of noise sources in reference voltage generator for very-high-speed pipelined ADC

A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers

Modified-filtered-x LMS algorithm based active noise control systems with improved online secondary-path modeling

General splitting and merging of 2-D DCT in the DCT domain

The determination of protein structures with a Gaussian objective function

Motion controlling in 2-D space using chaotic dynamics in a neural network with large redundancy

A ring type switched-capacitor (SC) programmable converter with DC or AC input/DC or AC output

Novel design procedure for MOSFET class E oscillator

Performance of UWB DS-CDMA/OFDM/MC-CDMA system

Digital assistable inverter-based band-pass filter

Current-mode universal biquadratic circuit using OTAs and DO-CCII

Low voltage fully differential CMOS current feedback operational amplifier

Low-voltage, rail-to-rail, G/sub m/-enhanced pseudo-differential class-AB OTA

An active-RC reconfigurable lowpass-polyphase Tow-Thomas biquad filter

A linear CMOS G/sub m/-C-OTA biquad filter with 10-100 MHz tuning

Operational transresistance amplifier based first-order allpass filter with an application example

Low voltage pseudo floating-gate all-pass filter

Generation of new OTA-C oscillator structures using network transposition

A pseudo-NMOS fully differential CMOS current-mode multiplexing transmitter for 10 Gb/s serial links

A high-speed high-resolution comparator

Design of a floating node voltage-controlled linear variable resistor circuit

A direct method for exact discretization of ordinary differential equations

Robust high-speed low input impedance CMOS current comparator

A dynamically controlled and refreshed low-power level-up shifter

On synthesis of reactance network shaping a monocycle pulse

A switched-voltage high-accuracy sample/hold circuit

A mixed equation-based and simulation-based design methodology for continuous-time sigma-delta modulators

Convergence problems and optimal parameter estimation in FFT-based method of numerical inversion of two-dimensional Laplace transforms

A channel-selection switched-capacitor filter with slew-rate enhancement operational amplifiers

Simulation of crosstalk through bonding and package in mixed-signal CMOS ICs

Design of a 1.8 V high frequency CMOS variable gain amplifier with a novel dB-linear gain structure

Design of a log-domain differentiator and integrator based universal analog biquadratic filter

Pseudo-differential integrator for UHF applications in digital CMOS technologies

A 1.25-Gb/s CMOS burst-mode optical receiver with automatic level restoration for PON applications

Performance evaluation of CMOS low drop-out voltage regulators

A precision CMOS sample-and-hold circuit with low temperature drift for integrated transducers

Design techniques for CMOS very-low-voltage operational amplifiers with enhanced power supply rejection ratio

A CMOS continuous-time FPAA analog core using automatically-tuned MOS resistors

Approach to high-linear programmable gain amplifiers

Optimized multi-stage minimum-distance-search circuit with feedback-stabilization for fully-parallel associative memories

An RF sampling downconversion filter for a receiver front-end

Modulation/demodulation scheme for high speed modem using matrix and inverse-matrix

Wideband-CDMA channel estimation: a data-aided multi-slot averaging method

Design of a concurrent dual-band receiver front-end in 0.18 /spl mu/m CMOS for WLANs IEEE 802.11a/b/g applications

An improved low voltage phase-frequency detector with extended frequency capability

CMOS low noise amplifier design optimization technique

Design of circular polarized antennas using genetic algorithm based on curved wire analysis

A high-linearity SiGe mixer ICs for 5-6 GHz wireless applications

Harmonic balance analysis of output impedance matching in active RF/microwave frequency multipliers

Harmonic balance analysis of input impedance matching in active RF/microwave frequency multipliers

Reducing spurious output of balanced modulators by dynamic matching of I, Q quadrature paths

Local thresholding of composite documents using multi-layer perceptron neural network

Color stereo matching based on self-organization neural networks

Rough segmentation of natural color images using fuzzy-based hierarchical algorithm

A method of face recognition using 3D images

Soft and hard biometrics fusion for improved identity verification

Measurement of pedestrian crossing length using vector geometry - an image based technique

Fast fractal encoding algorithm using the law of cosines

Vector quantization by a self-organizing tree with newly implemented pruning algorithm

An enhanced fast encoding method for vector quantization by constructing new feature based on the variances of subvectors

Lossless coding of color quantized images based on pseudo distance

Spatially unequal error protection in video coding for low SNR channels

Hierarchical human motion compression with constraints on frames

Scalable video transcoding method with spatial updatable scalability

An efficient contour-based algorithm for binary video shape coding

Packet loss recovery for RTP-based transmission of JPEG2000 images enabling backward compatibility with standard decoder

A study on the method to reduce data transfer in multi-quality VOD service

Development of digital image retrieval technique using autocorrelogram and wavelet based texture

Anisotropic shock filter for enhancement and non-photorealistic generation of flow patterns

An improvement of an adaptive weighted mean filter using fuzzy clustering

A simple edge-weighted image enhancement filter using wavelet scale products

Time and spatial /spl epsiv/-filter for improving image quality of compressed video

A change detection method for image sequences based on physical models

Semantic units detection and summarization of baseball videos

Flexibly configurable multivision remote monitoring system

Improvement of image quality by optical image processing suitable for pixel shape of display

Improvement of degraded picture quality due to scanning frequency difference between TV camera and PC display with CRT

Optimization of gray scale morphological opening for noise removal in texture images

Uniform converting matrix in photometric stereo shape reconstruction method

Arbitrary viewpoint image generation method of unknown objects in known environment using a single camera

Post modulator filtering in /spl Delta/-/spl Sigma/ fractional-N frequency synthesis

Filtering adjacent channel blockers using signal-transfer-function of continuous-time /spl Sigma//spl Delta/ modulators

A subtraction-based adder amplifier for 10b 50 MS/s low-power pipelined-ADC's

Time quantization derivative PWM based one-bit DPCM

Compensation of timing mismatches in time-interleaved analog-to-digital converters through transfer characteristics tuning

A high performance class-D amplifier with cascaded sigma-delta modulators

A novel genetic algorithm with applications to the design of higher-order sigma-delta D/A converters

14 b, 50 MS/s CMOS front-end sample and hold module dedicated to a pipelined ADC

Design techniques for a CMOS low-power low-voltage fully differential flash analog-to-digital converter

Measurement of distance and velocity of a moving target by short-range high-resolution radar utilizing standing wave

Mechatronic design of RF MEMS switches for communication applications

A multiple operation mode CMOS digital pixel sensor dedicated to a visual cortical implant

CMOS VCO & LNA implemented by air-suspended on-chip RF MEMS LC

Characterization of two opto-electronic structures for high-frequency applications

Analytical two-segment method to predict the chaotic phenomenon in nonlinear system

On stable patterns realized by a class of one-dimensional two-layer CNNs

Necessary and sufficient conditions for one-dimensional discrete-time binary cellular neural network with nonsymmetric connections to be stable

Analysis of drug sensitivity of ventricular myocardial ionic channels based on the global bifurcation structure

Curve search method for constrained global optimization

Using LDPC codes to enhance the performance of FM-DCSK

Electrical circuit representations of the neutron diffusion equations

Simple approximation models for coupled RC lines with application to delay and crosstalk estimation

Exact calculation of amplitudes and frequency of RC-oscillator with quadrature outputs

Identification of bifurcation parameters in switching power converter composed of cascade two-stage PFC circuit

A novel method to remove the mismatch of the up-conversion mixer for a low IF transmitter

Effects of demodulator errors on convergence time of look-up table based iterative algorithms for adaptive digital predistortion linearizer

Clusters first? A study of circuit structure and placement

A compact code for representing floorplans

A fast algorithm for rectilinear block packing based on selected sequence-pair

A methodology for performance driven incremental placement with high level exploration

Area reduction on interconnect optimized floorplan using deadspace utilization

Multilevel interconnect-driven floorplanner

Enhanced fault-tolerant CMOS memory elements

Analytical ramp delay model for distributed on-chip RLC interconnects

A simulated-annealing-based approach for timing-constrained flexibility-driven routing tree construction

A genetic algorithm for the rectilinear Steiner tree in 3-D VLSI layout design

Simultaneous wiring and buffer block planning with optimal wire-sizing for interconnect-driven floorplanning

A new routing design methodology for multi-chip IC packages

Parasitic-aware synthesis of RF LNA circuits considering quasi-static extraction of inductors and Interconnects

Analog module placement realizing symmetry constraints based on a radiation decoder

A layout-educated analog design flow

Analog-circuit-component optimization with genetic algorithm

A scheme to reduce active leakage power by detecting state transitions

Static variable ordering in ZBDDs for path delay fault coverage calculation

Debugging complex counterexample of hardware system using control flow distance metrics

Relationship between Hadamard-Haar and arithmetic transforms

Walsh-Hadamard spectral minimization of fixed polarity Reed-Muller expansions

Generalization of arithmetic-Haar transform for higher dimensions

Realization of sequential circuits by look-up table rings

Monotonic behavior refinement for synthesis of two-input-gate asynchronous circuits

An LUT-based error diagnosis technique improved in multiplicity of rectifiable errors

An optical reconfiguration circuit for optically reconfigurable gate arrays

New voltage level shifting circuits for low power CMOS interface applications

Meta-I/O interface using reconfigurable LSIs

Implementations of a hardware n choose k counter

High speed emulation of gene regulatory networks using FPGAs

Hardware implementation of genetic algorithms using FPGA

Variable-precision multiplier for equalizer with adaptive modulation

Test circuit for CMOS lead open detection by supply current testing under AC electric field application

Reference-pattern learning and optimization from an input-pattern stream for associative-memory-based pattern-recognition systems

Low power dual transmission gate adiabatic logic circuits and design of SRAM

Low power bank-based multi-port SRAM design due to bank standby mode

2003 46th Midwest Symposium on Circuits and Systems

The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002.

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)

42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356)

1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg

Proceedings of the 39th Midwest Symposium on Circuits and Systems

38th Midwest Symposium on Circuits and Systems. Proceedings

Proceedings of 1994 37th Midwest Symposium on Circuits and Systems

Proceedings of 36th Midwest Symposium on Circuits and Systems

[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems

[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems

Proceedings of the 33rd Midwest Symposium on Circuits and Systems

Proceedings of the 32nd Midwest Symposium on Circuits and Systems,

An enhanced fast encoding method for vector quantization by constructing new feature based on the variances of subvectors

Content Provider	IEEE Xplore Digital Library
Author	Zhibin Pan Kotani, K. Ohmi, T.
Copyright Year	2004
Description	Author affiliation: New Ind. Creation Hatchery Center, Tohoku Univ., Sendai, Japan (Zhibin Pan)
Abstract	The encoding process of vector quantization (VQ) is a time bottleneck to its practical applications due to it performing a lot of k-dimensional Euclidean distance computations. In order to speed up the process of VQ encoding, it is most important to avoid unnecessary exact Euclidean distance computations as many as possible. This purpose can be realized by first estimating how large Euclidean distance is with just a lighter computation, which requires the estimation for Euclidean distance must be less or equal to Euclidean distance itself. Then, if this estimation is sufficiently large, it can lead to a rejection to current candidate codeword. In order to make an estimation for Euclidean distance, appropriate features of vectors are necessary. By using famous statistical features (i.e. the sum and the variance) of a k-dimensional vector and its two corresponding (k/2)-dimensional subvectors to estimate Euclidean distance first, it is possible to reject most of unlikely codewords for a certain input vector as proposed in the previous works. Under the consideration of using the sum and the variance information as features of vectors, a new feature based on the variances of two subvectors is constructed in this paper to set up a new estimation for Euclidean distance. Meanwhile, a memory-efficiency data structure is proposed for storing all features of a vector to avoid any extra memory requirement compared to the latest previous work. Experimental results confirmed that the proposed search method in this paper is more search efficient.
File Size	768016
File Format	PDF
ISBN	078038346X
DOI	10.1109/MWSCAS.2004.1353971
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-07-25
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Encoding Vector quantization Euclidean distance Image coding Search methods Decoding Nearest neighbor searches Computer industry Electronic mail Data structures
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in