NDLI: An interleaved/pipelined architecture for adaptive lattice equalizer

Content Provider	IEEE Xplore Digital Library
Author	Fengqi Yu Willson Jr., A.N.
Copyright Year	2000
Description	Author affiliation: Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA (Fengqi Yu)
Abstract	It is well known that the convergence of least mean square (LMS) algorithms to the optimum filter coefficients is slow when the input samples are highly correlated. The adaptive lattice algorithm, a technique to overcome the slow LMS convergence problem, was proposed quite some time ago. However, due to its high complexity, it has not been widely implemented in silicon. In this paper we propose an interleaved architecture for implementing this algorithm. The proposed architecture is hardware efficient, including a reduction in the number of dividers from two to one. The hardware implementation of the proposed architecture is presented and its hardware complexity is estimated at the gate level. Without reducing throughput, the hardware complexity of the proposed architecture is approximately 66% that of the conventional adaptive lattice equalizer.
Starting Page	856
Ending Page	859
File Size	329060
Page Count	4
File Format	PDF
ISBN	0780364759
DOI	10.1109/MWSCAS.2000.952889
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-08-08
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Lattices Equalizers Convergence Least squares approximation Hardware Kalman filters Adaptive filters Reflection Laboratories Silicon
Content Type	Text
Resource Type	Article

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