NDLI: An algorithm and design to test random access memories

Content Provider	IEEE Xplore Digital Library
Author	Rajsuman, R.
Copyright Year	1992
Description	Author affiliation: Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA (Rajsuman, R.)
Abstract	A fast test generation algorithm of 7n complexity for testing RAMs, where n is the number of words, is presented. This algorithm covers 100% single cell stuck-at-1/0 faults, transition 1-to-0 and 0-to-1 faults, bridging faults between two cells (state coupling), and data retention faults. A design methodology (STD architecture) for designing large memories so that a very small test time can be achieved is also presented. The memory is partitioned into several small blocks. The memory address decoder is divided into two or more levels and designed so that in the test mode all small memory blocks can be accessed together. The hardware overhead in this approach is negligible, and a constant test time can be achieved irrespective of the memory size. The STD architecture is applicable to memory chips as well as memory boards.<>
Starting Page	439
Ending Page	442
File Size	367403
Page Count	4
File Format	PDF
ISBN	0780305930
DOI	10.1109/ISCAS.1992.229919
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-05-10
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Random access memory Hardware Built-in self-test Manufacturing Design methodology Automatic testing System testing Costs Decoding
Content Type	Text
Resource Type	Article

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