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VLSI architectures of two-dimensional filters for HDTV coding

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VLSI decompositions for deBruijn graphs

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VLSI decompositions for deBruijn graphs

Content Provider	IEEE Xplore Digital Library
Author	Dolinar, S. Ko, T.-M. McEliece, R.
Copyright Year	1992
Description	Author affiliation: California Inst. of Technol., Pasadena, CA, USA (Dolinar, S.; Ko, T.-M.; McEliece, R.)
Abstract	A C-chip VLSI decomposition of a graph G is a collection of C isomorphic disjoint subgraphs of G (the building blocks), which together contain all of G's vertices. The efficiency of such a decomposition is defined to be the fraction of edges of G that are in the building block. Motivated by the need to construct large Viterbi decoders, the authors study VLSI decompositions of deBruijn graphs. They obtain some strong necessary conditions for a graph to be a building block for a deBruijn graph, and some slightly more restrictive sufficient conditions which allow the construction of some efficient building blocks for deBruijn graphs.<>
Starting Page	1855
Ending Page	1858
File Size	320297
Page Count	4
File Format	PDF
ISBN	0780305930
DOI	10.1109/ISCAS.1992.230451
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-05-10
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Circuits Viterbi algorithm Decoding Wires Propulsion Laboratories Convolutional codes Sufficient conditions Computer networks
Content Type	Text
Resource Type	Article

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