NDLI: New graph-based algorithms for partitioning VLSI circuits

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2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

Volume 5 - 2004

Volume 4 - 2004

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Table of contents

A matched biphasic microstimulator for an implantable retinal prosthetic device

Low-power implantable microsystem intended to multichannel cortical recording

Design of a low-power, implantable electromyogram amplifier

A wavelet based R-wave detector for cardiac pacemakers in 0.35 CMOS technology

A closed loop transcutaneous power transfer system for implantable devices with enhanced stability

A low noise CMOS amplifier for ENG signals

Integrated multi-electrode fluidic nitric-oxide sensor and VLSI potentiostat array

A low-power CMOS neural amplifier with amplitude measurements for spike sorting

Low noise amplifier for recording ENG signals in implantable systems

A low-power implantable Pseudo-BJT-based silicon retina with solar cells for artificial retinal prostheses

An efficient inductive power link design for retinal prosthesis

Craniofacial landmarks extraction by Partial Least Squares Regression

Fuzzy vector filters for microarray image enhancement

CMOS microelectrode array for extracellular stimulation and recording of electrogenic cells

A C-less ASK demodulator for implantable neural interfacing chips

A comparison of two similarity measures in intensity-based ultrasound image registration

Nonlinear techniques and neural activity: emergent trends in MEG data

A novel representation method for electromyogram (EMG) signal with predefined signature and envelope functional bank

Memory optimization techniques for UMTS code generation

Low complexity System-on-Chip architectures of Parallel-Residue-Compensation in CDMA systems

Power efficient architecture for (3,6)-regular low-density parity-check code decoder

An efficient architecture for peak-to-average power ratio reduction in OFDM systems in the presence of pulse-shaping filtering

An efficient memory compression scheme for 8 k FFT in a DVB-T receiver and the corresponding error model

A novel multipath searcher implementation for WCDMA receivers

Low power flexible Rake receivers for WCDMA

A simple STF-OFDM transmission scheme with maximum frequency diversity gain

Low-power design for cell search in W-CDMA

Improvement of fuzzy power control for DS-CDMA cellular mobile system having variable number of users

Analysis of higher-order N-tone sigma-delta modulators for ultra wideband communications

3-state pseudorandom noise (PN) sequence 3-pulse Reference Sharing Ultra Wideband System

Reference Sharing Ultra Wideband Communication System

Design of a low-complexity receiver for impulse-radio ultra-wideband communication systems

A CMOS impulse generator for UWB wireless communication systems

The design of a 14 GHz I/Q ring oscillator in 0.18 /spl mu/m CMOS

A mutual-negative-resistance quadrature CMOS LC oscillator

Analysis of oscillator amplitude control, and its application to automatic tuning of quality factor for active LC filters

A wide tuning range VCO using capacitive source degeneration

Behavior modelling for LC tank based oscillators

On the design of an offset-PLL modulation loop for the EGSM band

Phase Locked Loop gain shaping for gigahertz operation

Phase-locked loop architecture for adaptive jitter optimization

Fast-switching analog PLL with finite-impulse response

A novel ultra high-speed flip-flop-based frequency divider

Reed-Solomon behavioral virtual component for communication systems

A high throughput limited search trellis decoder for convolutional code decoding

A low-power, hard-decision analogue convolutional decoder using the modified feedback decoding algorithm

A new digital signature scheme

Scaleable check node centric architecture for LDPC decoder

Direct Sigma Delta GMSK modulator modeling and design for 2.5 G TX applications

A radio-frequency CMOS active inductor and its application in designing high-Q filters

Implementation of novel sampling and reconstruction circuits in digital radios

A high speed trans-impedance amplifier using 0.13 /spl mu/m triple-well CMOS technology

6.8 mW 2.5 Gb/s and 42.5 mW 5 Gb/s 1:8 CMOS demultiplexers

Four-channel SiGe transimpedance amplifier array for parallel optical interconnects

CMOS limiting optical preamplifiers using dynamic biasing for wide dynamic range

Improved multicast switch architecture for optical cable television and video surveillance networks

Rapid bit-error-rate measurements of infrared communication systems

Efficient analysis of multilayered broadside edge-coupled anisotropic structures for microwave applications

Direct digital frequency synthesizer with multi-stage linear interpolation

A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time

High-speed RF multi-modulus prescaler architecture for /spl Sigma/-/spl Delta/ fractional-N PLL frequency synthesizers

A new prescaler for fully integrated 5-GHz CMOS frequency synthesizer

A 5-GHz delta-sigma PLL frequency synthesizer for WLAN applications

CMOS integrated transformer-feedback Q-enhanced LC bandpass filter for wireless receivers

An IIP2 calibration technique for direct conversion receivers

UMTS/GSM multi mode receiver design

A CMOS multi-standard receiver architecture for ISM and UNII band applications

A 5 GHz direct-conversion receiver with DC offset correction

Gain bandwidth considerations in fully integrated distributed amplifiers implemented in silicon

An exact analysis of Class-E power amplifiers for RF communications

A power constrained simultaneous noise and input matched low noise amplifier design technique

Inductive peaking in wideband CMOS current amplifiers

A DC-6 GHz, 50 dB dynamic range, SiGe HBT true logarithmic amplifier

A 5-Gb/s 1/8-rate CMOS clock and data recovery circuit

A high-speed low-voltage phase detector for clock recovery from NRZ data

A CMOS 10 Gb/s clock and data recovery circuit with a novel adjustable K/sub pd/ phase detector

A 1/8-rate clock and data recovery architecture for high-speed communication systems

An interpolation filter based on spline functions for non-synchronized timing recovery

A linearization technique for RF low noise amplifier

A self-synchronized RF-interconnect for 3-dimensional integrated circuits

2.4 GHz RF down-conversion mixers in standard CMOS technology

A 0.18 /spl mu/m CMOS 900 MHz receiver front-end using RF Q-enhanced filters

Adaptable MOS current mode logic for use in a multi-band RF prescaler

A novel memoryless AES cipher architecture for networking applications

Coupling effects in an integrated beam-forming transmitter

Enhanced Parallel Interference Cancellation using Decorrelator for the base-station receiver

Digital receiver architectures for the IEEE 802.15.4 standard

Transceiver circuits for pulse-based ultra-wideband

Design and comparison of CMOS Current Mode Logic latches

A fast-lock DLL with power-on reset circuit

High-speed and wide-tuning-range LC frequency dividers

Improving the acquisition time of a PLL-based, integer-N frequency synthesizer

Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector

A novel 1.5 V CMFB CMOS down-conversion mixer design for IEEE 802.11 A WLAN systems

A CMOS low power buffer based bandpass IF filter for Bluetooth

Bandpass sigma-delta (/spl Sigma/-/spl Delta/) architecture based efficient FM demodulator for software radio

A low-power low-voltage NMOS bulk-mixer with 20 GHz bandwidth in 90 nm CMOS

A simple and robust super-regenerative oscillator for the 2.4 GHz ISM band

A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier

Simultaneous bidirectional signaling with adaptive pre-emphasis

1000BASE-T Gigabit Ethernet baseband DSP IC design

A new full CMOS 2.5 V two-stage line driver with variable gain for ADSL applications

A class A/B low power amplifier for wireless sensor networks

Characteristics and modeling of a broadband transmission-line transformer

A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications

A low-power, 10 GHz back-gated tuned voltage controlled oscillator with automatic amplitude and temperature compensation

Jitter in high-speed serial and parallel links

Experimental results of a type-based predistorter for SSPA linearization

R&D platform for man scale wireless AD HOC networks towards a hardware demonstrator for 4G+ systems

Optimization method for designing filter bank channelizer of a software defined radio using vertical common subexpression elimination

A low-power crosstalk-insensitive signaling scheme for chip-to-chip communication

Power spectral density of Transmit Reference Doublet trains and Reference Sharing Doublet trains in ultra wideband systems

Burst receiver for upstream communications over twisted pair lines

A novel I/Q mismatch compensation scheme for a low-IF receiver front-end

Tunable matching networks for future MEMS-based transceivers

On various low-hardware-complexity LMS algorithms for adaptive I/Q correction in quadrature receivers

A new NDA timing error detector for BPSK and QPSK with an efficient hardware implementation for ASIC-based and FPGA-based wireless receivers

A CMOS-MEMS magnetic thin-film inductor for radio frequency and intermediate frequency filter circuits

Differentiating network conversation flow for intrusion detection and diagnostics

VLSI implementation issues of lattice decoders for MIMO systems

A calibration method for PLLs based on transient response

Modeling and diagnosis of analog circuits with probabilistic graphical models

A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects

On relation between non-disjoint decomposition and multiple-vertex dominators

Studies on distributed algorithm for network flow optimization problem based on tie-set flow vector space

Unfolding of Petri nets with semilinear reachability set

S-sequence: a new floorplan representation method preserving room abutment relationships

Calculation of non-mixed second derivatives in multirate systems through signal flow graph techniques

Chaotic sequences in ACO algorithms

Construction of linearly transformed planar BDD by Walsh coefficients

New graph-based algorithms for partitioning VLSI circuits

Multi-layer constrained via minimization with conjugate conflict continuation graphs

A comparison of graph coloring heuristics for register allocation based on coalescing in interval graphs

A low phase noise 2.0 V 900 MHz CMOS voltage controlled ring oscillator

Single ended rail-to-rail CMOS OTA based variable-frequency ring-oscillator

A precise 90/spl deg/ quadrature OTA-C VCO between 50-130 MHz

A 2.4 GHz low-power low-phase-noise CMOS VCO using spiral inductors and junction varactors

Fully current controllable AM/FM modulator and quadrature sinusoidal oscillator based on CCCIIs

Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture

Spectral shaping by generalized transfer function design in frequency modulation /spl Sigma//spl Delta/ synthesizers

The design of a differential CMOS charge pump for high performance phase-locked loops

Frequency synthesizer for on-chip testing and automated tuning

An ADPLL circuit using a DDPS for genlock applications

Resonance properties of Chebyshev chaotic sequences

RSA encryption algorithm based on torus automorphisms

A double scroll based true random bit generator

Post-processing of data generated by a chaotic pipelined ADC for the robust generation of perfectly random bitstreams

A novel CFAR intrusion detection method using chaotic stochastic resonance

Optimal chaos shift keying communications with correlation decoding

Optimum noncoherent FM-DCSK detector: application of chaotic GML decision rule

Generalized correlation-delay-shift-keying scheme for noncoherent chaos-based communication systems

An improved multiple access scheme for chaos-based digital communications using adaptive receivers

On distributions of multiple access interference for spread spectrum communication systems using M-phase spreading sequences of Markov chains

Pulse shaping and SIR-energy trade-off in chaos-based asynchronous DS-CDMA

Markovian SS codes imply inversion-free code acquisition in asynchronous DS/CDMA systems

A practical algorithm for turbo-decoding enhancement

Analysis and effects of retransmission mechanisms on data network performance

Analysis of Internet topology data

Distortion analysis of nonlinear networks based on SPICE-oriented harmonic balance method

A tool for the integration of new VHDL-AMS models in SPICE

Event-driven simulation and modeling of an RF oscillator

Fitting of 2-dimensional polynomial device model based on simulated voltage and current spectra

Simple RC models of distributed RC lines in consideration with the delay time

Polyphase representation of multirate Volterra filters

Nonlinear dynamics of gear-shifting digital phase-locked loops

A novel method for identifying cubically nonlinear systems using minimally bandpass sampled data

PWL identification of dynamical systems: some examples

Pattern detection in noisy signals

Spike position map with quantized state and its application to algorithmic A/D converter

Sigma-Delta A/D fuzzy converter

Noise robustness condition for chaotic maps with piecewise constant invariant density

Structure and information content in sequences from the single-loop sigma-delta modulator with DC input

Spectral aliasing effects of PWM signals with time-quantized switching instants

Hopf-like transitions in nonsmooth dynamical systems

Grazing bifurcations in periodic hybrid systems

Analysis of bifurcation in switched dynamical systems with periodically moving borders: application to power converters

Controlling limit cycles in planar dynamical systems: a nonsmooth bifurcation approach

Dither for chattering reduction in sliding mode control systems

Pulse-excited RC nonautonomous chaotic oscillator structures

Towards full characterization of continuous systems in terms of periodic orbits

A binary-quantized pseudo-diffusion system

Synchronization in systems coupled via complex networks

Global adaptive synchronization based upon polytopic observers

Chaos control in permanent magnet synchronous motor

Self-induced oscillations in coupled fluxgate magnetometer: a novel approach to operating the magnetic sensors

Design of bursting in two-dimensional discrete-time neuron models

Low power real time electronic neuron VLSI design using subthreshold technique

Linearization of CMOS LNA's via optimum gate biasing

A low power and high speed CMOS Voltage-Controlled Ring Oscillator

Design and implementation of CMOS distributed mixers and oscillators for wide-band RF front-end

Novel architectures of class AB CMOS mirrors with programmable gain

Two low-voltage high-speed CMOS frequency-insensitive PWM signal generators based on relaxation oscillator

A closed-form phase noise solution for an ideal LC oscillator

Stability analysis of power circuit comprising virtual inductance

An unlimited lock range DLL for clock generator

Design and simulation of Fractional-N PLL frequency synthesizers

Maintaining chaos in an associative chaotic neural network exhibiting intermittency

A mixed PLL/DLL architecture for low jitter clock generation

Experimental evidence for amplitude death induced by dynamic coupling: van der Pol oscillators

Bifurcation analysis in a piecewise-smooth system with periodic threshold

On the synchronization region in networks of coupled oscillators

Nonlinear dynamics of a nonideal sigma-delta modulator with periodic input

Hyperreal operating points for nonlinear transfinite networks

Robust three-state PFD architecture with enhanced frequency acquisition capabilities

Two-sided projection method in variational equation model order reduction of nonlinear circuits

Small world effects in networks: an engineering interpretation

A time-to-first spike CMOS imager

Second generation of high dynamic range, arbitrated digital imager

Analog integrated circuit for detection of approaching object against moving background based on lower animal vision

Adaptive multiple resolution CMOS active pixel sensor

A time-based CMOS image sensor

Self-biasing low power adaptive photoreceptor

Normal Optical Flow measurement on a CMOS APS imager

High speed and high resolution current winner-take-all circuit in conjunction with adaptive thresholding

An electronic calibration scheme for logarithmic CMOS pixels

Linear current mode imager with low fix pattern noise

A circuit to model an Ionic Polymer-Metal Composite as actuator

Highly sensitive silicon micro-g accelerometers with optical output

Detection and compensation of sensor malfunction in time delay based direction of arrival estimation

An RF powered, wireless temperature sensor in quarter micron CMOS

Silicon on sapphire CMOS architectures for interferometric array readout

Bearing angle estimation for sonar micro-array using analog VLSI spatiotemporal processing

A monolithic fully-differential CMOS gas sensor microsystem for microhotplate temperatures up to 450/spl deg/C

A low-voltage, chemical sensor interface for systems-on-chip: the fully-differential potentiostat

A mixed-mode temperature control circuit for gas sensors

A VLSI model of the bat lateral superior olive for azimuthal echolocation

Clustering routing algorithm using game-theoretic techniques for WSNs

Toward a circuit theory for sensor networks with fading channels

A 2-Mb/s, UHF-band, wireless sensor node for real-time multi-point sensing

Electrical connectivity analysis of a MEMS micropackage

Surface micromachining in Silicon on Sapphire CMOS technology

A 2-Dimensional active cochlear model for analog VLSI implementation

An alternative analog VLSI implementation of the Meddis inner hair cell model

Elimination of quantization effects in measured temporal noise

Charge-based prediction circuits for focal plane image compression

Minimization of power dissipation of analog channel-select filter and Nyquist-rate A/D converter in UTRA/FDD

A single-chip CMOS visual orientation sensor

A high speed centroid computation circuit in analog VLSI

Minipix: focal plane temporal frequency image processor

ALOHA CMOS imager

CMOS APS imager employing 3.3 V 12 bit 6.3 MS/s pipelined ADC

ISCAS 2004 Proceedings Author Index

Volume 3 - 2004

Volume 2 - 2004

Volume 1 - 2004

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003.

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

1993 IEEE International Symposium on Circuits and Systems

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems

1991., IEEE International Sympoisum on Circuits and Systems

IEEE International Symposium on Circuits and Systems

IEEE International Symposium on Circuits and Systems,

1988., IEEE International Symposium on Circuits and Systems

New graph-based algorithms for partitioning VLSI circuits

Content Provider	IEEE Xplore Digital Library
Author	Augeri, C.J. Ali, H.H.
Copyright Year	2004
Description	Author affiliation: Dept. of Comput. Sci., US Air Force Acad., CO, USA (Augeri, C.J.)
Abstract	When designing a circuit, it may be too large to fit on a single layer of a chip, on a single chip, or on a single board. Regardless of the design level, the same objectives remain. Normally, it is desirable to minimize the number of layers, chips, or boards, along with minimizing the delay. Additional constraints, such as the number of interconnections and power consumption, must often be considered. We have developed two k-way bounded partitioning algorithms; one is evolutionary-based, while the other is a hierarchical graph center-based approach. The algorithms are implemented and compared with known partitioning algorithms. Since VLSI circuits can be naturally modeled by graphs, experiments were conducted by partitioning graphs from various graph families against both simulated and real-world partitioning criteria. A direct result of this research is a high-level abstract graph-partitioning model. This model allows one to specify mathematical evaluation metrics and control parameters, permitting inter-domain comparison of algorithms and allowing one to identify the particular scenarios they are best applicable to.
Sponsorship	IEEE Circuits and Syst. Soc
File Size	266519
File Format	PDF
ISBN	078038251X
DOI	10.1109/ISCAS.2004.1329055
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-05-23
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Partitioning algorithms Very large scale integration Delay Clustering algorithms Computer science Wire Integrated circuit interconnections Energy consumption Circuit simulation Mathematical model
Content Type	Text
Resource Type	Article

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