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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wei Wang Swamy, M.N.S. Ahmad, M.O. |
| Copyright Year | 2002 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada (Wei Wang; Swamy, M.N.S.; Ahmad, M.O.) |
| Abstract | In this paper, a new architecture of a redundant residue number system (RRNS) quasi-chaotic (QC) encoder/decoder with an error-correcting ability is proposed for secure communication and is tailored to FPGA implementation. In the proposed architecture, binary subencoders and subdecoders are used so that a number of modulo operations required in the existing design of D. R. Frey (IEEE Trans. Circuits Syst. II, vol. 40, pp. 660-666, Oct. 2000) are replaced by a simple truncation. Furthermore, a size-reduced design of the R/B (residue-to-binary) converter with error-correcting function, which is the crucial part of the system, is proposed. As a case study, the proposed architecture is implemented in FPGA for the case of the 16-bit input and some simulation results obtained. |
| Sponsorship | IEEE IEEE Circuits & Syst. Soc |
| File Size | 362847 |
| File Format | |
| ISBN | 0780374487 |
| DOI | 10.1109/ISCAS.2002.1010828 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2002-05-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Decoding Field programmable gate arrays Chaotic communication Computer architecture Computer errors Multiaccess communication Filters Application specific integrated circuits Equations Signal processing |
| Content Type | Text |
| Resource Type | Article |
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